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Message-Id: <20200322110028.18279-8-alex@ghiti.fr>
Date: Sun, 22 Mar 2020 07:00:28 -0400
From: Alexandre Ghiti <alex@...ti.fr>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Zong Li <zong.li@...ive.com>, Anup Patel <anup@...infault.org>,
Christoph Hellwig <hch@....de>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: Alexandre Ghiti <alex@...ti.fr>
Subject: [RFC PATCH 7/7] riscv: Explicit comment about user virtual address space size
Define precisely the size of the user accessible virtual space size
for sv32/39/48 mmu types and explain why the whole virtual address
space is split into 2 equal chunks between kernel and user space.
Signed-off-by: Alexandre Ghiti <alex@...ti.fr>
---
arch/riscv/include/asm/pgtable.h | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 06361db3f486..be117a0b4ea1 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -456,8 +456,15 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
/*
- * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32.
- * Note that PGDIR_SIZE must evenly divide TASK_SIZE.
+ * Task size is:
+ * - 0x9fc00000 (~2.5GB) for RV32.
+ * - 0x4000000000 ( 256GB) for RV64 using SV39 mmu
+ * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu
+ *
+ * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V
+ * Instruction Set Manual Volume II: Privileged Architecture" states that
+ * "load and store effective addresses, which are 64bits, must have bits
+ * 63–48 all equal to bit 47, or else a page-fault exception will occur."
*/
#ifdef CONFIG_64BIT
#define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2)
--
2.20.1
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