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Message-Id: <1584904058-53155-7-git-send-email-zhouyanjie@wanyeetech.com>
Date: Mon, 23 Mar 2020 03:07:37 +0800
From: 周琰杰 (Zhou Yanjie)
<zhouyanjie@...yeetech.com>
To: linux-clk@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
sboyd@...nel.org, mturquette@...libre.com, robh+dt@...nel.org,
mark.rutland@....com, paul@...pouillou.net,
dongsheng.qiu@...enic.com, yanfei.li@...enic.com,
sernia.zhou@...mail.com, zhenwenjin@...il.com
Subject: [PATCH v7 5/6] dt-bindings: clock: Add and reorder ABI for X1000.
1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not
directly derived from the output of SSIPLL, but from the clock
obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2"
is added for this purpose, it must between "X1000_CLK_SSIPLL"
and "X1000_CLK_SSIMUX", otherwise an error will occurs when
initializing the clock. These ABIs are only used for X1000, and
I'm sure that no other devicetree out there is using these ABIs,
so we should be able to reorder them.
2.Clocks of LCD, OTG, EMC, EFUSE, OST are also added.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
Acked-by: Rob Herring <robh@...nel.org>
---
Notes:
v5:
New patch.
v5->v6:
Add missing part of X1000's CGU.
v6->v7:
No change.
include/dt-bindings/clock/x1000-cgu.h | 62 +++++++++++++++++++----------------
1 file changed, 34 insertions(+), 28 deletions(-)
diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h
index bbaebaf..ef6ff63 100644
--- a/include/dt-bindings/clock/x1000-cgu.h
+++ b/include/dt-bindings/clock/x1000-cgu.h
@@ -12,33 +12,39 @@
#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
-#define X1000_CLK_EXCLK 0
-#define X1000_CLK_RTCLK 1
-#define X1000_CLK_APLL 2
-#define X1000_CLK_MPLL 3
-#define X1000_CLK_SCLKA 4
-#define X1000_CLK_CPUMUX 5
-#define X1000_CLK_CPU 6
-#define X1000_CLK_L2CACHE 7
-#define X1000_CLK_AHB0 8
-#define X1000_CLK_AHB2PMUX 9
-#define X1000_CLK_AHB2 10
-#define X1000_CLK_PCLK 11
-#define X1000_CLK_DDR 12
-#define X1000_CLK_MAC 13
-#define X1000_CLK_MSCMUX 14
-#define X1000_CLK_MSC0 15
-#define X1000_CLK_MSC1 16
-#define X1000_CLK_SSIPLL 17
-#define X1000_CLK_SSIMUX 18
-#define X1000_CLK_SFC 19
-#define X1000_CLK_I2C0 20
-#define X1000_CLK_I2C1 21
-#define X1000_CLK_I2C2 22
-#define X1000_CLK_UART0 23
-#define X1000_CLK_UART1 24
-#define X1000_CLK_UART2 25
-#define X1000_CLK_SSI 26
-#define X1000_CLK_PDMA 27
+#define X1000_CLK_EXCLK 0
+#define X1000_CLK_RTCLK 1
+#define X1000_CLK_APLL 2
+#define X1000_CLK_MPLL 3
+#define X1000_CLK_SCLKA 4
+#define X1000_CLK_CPUMUX 5
+#define X1000_CLK_CPU 6
+#define X1000_CLK_L2CACHE 7
+#define X1000_CLK_AHB0 8
+#define X1000_CLK_AHB2PMUX 9
+#define X1000_CLK_AHB2 10
+#define X1000_CLK_PCLK 11
+#define X1000_CLK_DDR 12
+#define X1000_CLK_MAC 13
+#define X1000_CLK_LCD 14
+#define X1000_CLK_MSCMUX 15
+#define X1000_CLK_MSC0 16
+#define X1000_CLK_MSC1 17
+#define X1000_CLK_OTG 18
+#define X1000_CLK_SSIPLL 19
+#define X1000_CLK_SSIPLL_DIV2 20
+#define X1000_CLK_SSIMUX 21
+#define X1000_CLK_EMC 22
+#define X1000_CLK_EFUSE 23
+#define X1000_CLK_SFC 24
+#define X1000_CLK_I2C0 25
+#define X1000_CLK_I2C1 26
+#define X1000_CLK_I2C2 27
+#define X1000_CLK_UART0 28
+#define X1000_CLK_UART1 29
+#define X1000_CLK_UART2 30
+#define X1000_CLK_SSI 31
+#define X1000_CLK_OST 32
+#define X1000_CLK_PDMA 33
#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
--
2.7.4
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