linux-kernel - RE: [PATCH v2 2/2] x86/delay: Introduce TPAUSE delay

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Message-ID: <3658BA65DD26AF4BA909BEB2C6DF6181A2A624C9@ORSMSX102.amr.corp.intel.com>
Date:   Mon, 23 Mar 2020 05:18:36 +0000
From:   "Park, Kyung Min" <kyung.min.park@...el.com>
To:     Joe Perches <joe@...ches.com>, "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:     "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "hpa@...or.com" <hpa@...or.com>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "ak@...ux.intel.com" <ak@...ux.intel.com>,
        "Luck, Tony" <tony.luck@...el.com>,
        "Raj, Ashok" <ashok.raj@...el.com>,
        "Shankar, Ravi V" <ravi.v.shankar@...el.com>,
        "Yu, Fenghua" <fenghua.yu@...el.com>
Subject: RE: [PATCH v2 2/2] x86/delay: Introduce TPAUSE delay

Hi Joe,

> -----Original Message-----
> From: Joe Perches <joe@...ches.com>
> Sent: Friday, March 20, 2020 3:07 AM
> To: Park, Kyung Min <kyung.min.park@...el.com>; x86@...nel.org; linux-
> kernel@...r.kernel.org
> Cc: tglx@...utronix.de; mingo@...hat.com; hpa@...or.com;
> gregkh@...uxfoundation.org; ak@...ux.intel.com; Luck, Tony
> <tony.luck@...el.com>; Raj, Ashok <ashok.raj@...el.com>; Shankar, Ravi V
> <ravi.v.shankar@...el.com>; Yu, Fenghua <fenghua.yu@...el.com>
> Subject: Re: [PATCH v2 2/2] x86/delay: Introduce TPAUSE delay
> 
> On Thu, 2020-03-19 at 21:13 -0700, Kyung Min Park wrote:
> > TPAUSE instructs the processor to enter an implementation-dependent
> > optimized state. The instruction execution wakes up when the
> > time-stamp counter reaches or exceeds the implicit EDX:EAX 64-bit input value.
> > The instruction execution also wakes up due to the expiration of the
> > operating system time-limit or by an external interrupt or exceptions
> > such as a debug exception or a machine check exception.
> []
> > diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c
> []
> > @@ -97,6 +97,27 @@ static void delay_tsc(u64 cycles)  }
> >
> >  /*
> > + * On Intel the TPAUSE instruction waits until any of:
> > + * 1) the TSC counter exceeds the value provided in EAX:EDX
> > + * 2) global timeout in IA32_UMWAIT_CONTROL is exceeded
> > + * 3) an external interrupt occurs
> > + */
> > +static void delay_halt_tpause(u64 start, u64 cycles) {
> > +	u64 until = start + cycles;
> > +	unsigned int eax, edx;
> > +
> > +	eax = (unsigned int)(until & 0xffffffff);
> > +	edx = (unsigned int)(until >> 32);
> 
> trivia:
> 
> perhaps lower_32_bits and upper_32_bits

Thank you for your comment. I'll update in the next patch.