linux-kernel - Two questions about cache coherency on arm platforms

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Message-ID: <20200323123524.w67fici6oxzdo665@mail.google.com>
Date:   Mon, 23 Mar 2020 20:35:26 +0800
From:   Changbin Du <changbin.du@...il.com>
To:     linux-arm-kernel@...ts.infradead.org
Cc:     changbin.du@...il.com, linux-kernel@...r.kernel.org
Subject: Two questions about cache coherency on arm platforms

Hi, All,
I am not very familiar with ARM processors. I have two questions about
cache coherency. Could anyone help me?

1. How is cache coherency maintenanced on ARMv8 big.LITTLE system?
As far as I know, big cores and little cores are in seperate clusters on
big.LITTLE system. And cache coherence betwwen clusters requires the
memory regions are marked as 'Outer Shareable' and is very expensive.
I have checked the kernel code, and seems it only requires coherence in
'Inner Shareable' domain. So my question is how can linux guarantees
cache coherence in 'CPU migration' or 'Global Task Scheduling' models
wich both clusters are active at the same time? For example, a thread
ran in Cluster A and modified 'Inner Shareable' memory, then it migrates
to Cluster B.

2. ARM64 cache maintenance code sync_icache_aliases() for non-aliasing icache.
In linux kernel on arm64 platform, the flow function sync_icache_aliases()
is used to sync i-cache and d-cache. I understand the aliasing case. but
for non-aliasing case why it just does "dc cvau" (in __flush_icache_range())
whithout really invalidate the icache? Will i-cache refill from L2 cache?

void sync_icache_aliases(void *kaddr, unsigned long len)
{
	unsigned long addr = (unsigned long)kaddr;

	if (icache_is_aliasing()) {
		__clean_dcache_area_pou(kaddr, len);
		__flush_icache_all();
	} else {
		/*
		 * Don't issue kick_all_cpus_sync() after I-cache invalidation
		 * for user mappings.
		 */
		__flush_icache_range(addr, addr + len);
	}
}

-- 
Cheers,
Changbin Du