linux-kernel - [PATCH net-next v7 08/10] net: phy: use phy_read_poll

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Message-Id: <20200323150600.21382-9-zhengdejin5@gmail.com>
Date:   Mon, 23 Mar 2020 23:05:58 +0800
From:   Dejin Zheng <zhengdejin5@...il.com>
To:     andrew@...n.ch, f.fainelli@...il.com, hkallweit1@...il.com,
        linux@...linux.org.uk, davem@...emloft.net, corbet@....net,
        tglx@...utronix.de, gregkh@...uxfoundation.org,
        allison@...utok.net, mchehab+samsung@...nel.org,
        netdev@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, Dejin Zheng <zhengdejin5@...il.com>
Subject: [PATCH net-next v7 08/10] net: phy: use phy_read_poll_timeout() to simplify the code

use phy_read_poll_timeout() to replace the poll codes for
simplify the code in phy_poll_reset() function.

Reviewed-by: Andrew Lunn <andrew@...n.ch>
Signed-off-by: Dejin Zheng <zhengdejin5@...il.com>
---
v6 -> v7:
	- adapt to a newly added parameter sleep_before_read.
v5 -> v6:
	- add some check for keep the code more similar.
v4 -> v5:
	- it can add msleep before call phy_read_poll_timeout()
	  to keep the code more similar. so add it.
v3 -> v4:
	- drop it.
v2 -> v3:
	- adapt to it after modifying the parameter order of the
	  newly added function
v1 -> v2:
	- remove the handle of phy_read()'s return error.

 drivers/net/phy/phy_device.c | 16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index a585faf8b844..3b8f6b0b47b5 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -1059,18 +1059,12 @@ EXPORT_SYMBOL(phy_disconnect);
 static int phy_poll_reset(struct phy_device *phydev)
 {
 	/* Poll until the reset bit clears (50ms per retry == 0.6 sec) */
-	unsigned int retries = 12;
-	int ret;
-
-	do {
-		msleep(50);
-		ret = phy_read(phydev, MII_BMCR);
-		if (ret < 0)
-			return ret;
-	} while (ret & BMCR_RESET && --retries);
-	if (ret & BMCR_RESET)
-		return -ETIMEDOUT;
+	int ret, val;
 
+	ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
+				    50000, 600000, true);
+	if (ret)
+		return ret;
 	/* Some chips (smsc911x) may still need up to another 1ms after the
 	 * BMCR_RESET bit is cleared before they are usable.
 	 */
-- 
2.25.0