linux-kernel - [PATCH 5.5 112/119] Revert "drm/i915/tgl: Add extra hdc flush workaround"

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Message-Id: <20200324130818.893795206@linuxfoundation.org>
Date:   Tue, 24 Mar 2020 14:11:37 +0100
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, Matt Roper <matthew.d.roper@...el.com>,
        Caz Yokoyama <caz.yokoyama@...el.com>,
        José Roberto de Souza <jose.souza@...el.com>,
        Jani Nikula <jani.nikula@...el.com>
Subject: [PATCH 5.5 112/119] Revert "drm/i915/tgl: Add extra hdc flush workaround"

From: Caz Yokoyama <caz.yokoyama@...el.com>

commit c09f6b4d0883dfb859c1ddcfb04c3260ef310ce0 upstream.

This reverts commit 36a6b5d964d995b536b1925ec42052ee40ba92c4.

The commit takes care Wa_1604544889 which was fixed on a0 stepping based on
a0 replan. So no SW workaround is required on any stepping now.

Reviewed-by: Matt Roper <matthew.d.roper@...el.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@...el.com>
Signed-off-by: José Roberto de Souza <jose.souza@...el.com>
Fixes: 36a6b5d964d9 ("drm/i915/tgl: Add extra hdc flush workaround")
Link: https://patchwork.freedesktop.org/patch/msgid/1c751032ce79c80c5485cae315f1a9904ce07cac.1583359940.git.caz.yokoyama@intel.com
(cherry picked from commit 175c4d9b3b9a60b4ea0b8cd034011808c6a03b05)
Signed-off-by: Jani Nikula <jani.nikula@...el.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>

---
 drivers/gpu/drm/i915/gt/intel_lrc.c |   20 --------------------
 1 file changed, 20 deletions(-)

--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3503,26 +3503,6 @@ static int gen12_emit_flush_render(struc
 
 		*cs++ = preparser_disable(false);
 		intel_ring_advance(request, cs);
-
-		/*
-		 * Wa_1604544889:tgl
-		 */
-		if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) {
-			flags = 0;
-			flags |= PIPE_CONTROL_CS_STALL;
-			flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
-
-			flags |= PIPE_CONTROL_STORE_DATA_INDEX;
-			flags |= PIPE_CONTROL_QW_WRITE;
-
-			cs = intel_ring_begin(request, 6);
-			if (IS_ERR(cs))
-				return PTR_ERR(cs);
-
-			cs = gen8_emit_pipe_control(cs, flags,
-						    LRC_PPHWSP_SCRATCH_ADDR);
-			intel_ring_advance(request, cs);
-		}
 	}
 
 	return 0;