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Message-ID: <048701d6047a$8752f390$95f8dab0$@gmail.com>
Date: Fri, 27 Mar 2020 21:58:53 +0100
From: <ansuelsmth@...il.com>
To: "'Bjorn Andersson'" <bjorn.andersson@...aro.org>
Cc: "'Andy Gross'" <agross@...nel.org>,
"'Ajay Kishore'" <akisho@...eaurora.org>,
"'Linus Walleij'" <linus.walleij@...aro.org>,
<linux-arm-msm@...r.kernel.org>, <linux-gpio@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: R: [PATCH v2] pinctrl: qcom: use scm_call to route GPIO irq to Apps
> On Thu 26 Mar 10:35 PDT 2020, Ansuel Smith wrote:
>
> > From: Ajay Kishore <akisho@...eaurora.org>
> >
> > For IPQ806x targets, TZ protects the registers that are used to
> > configure the routing of interrupts to a target processor.
> > To resolve this, this patch uses scm call to route GPIO interrupts
> > to application processor. Also the scm call interface is changed.
> >
> > Signed-off-by: Ajay Kishore <akisho@...eaurora.org>
> > Signed-off-by: Ansuel Smith <ansuelsmth@...il.com>
>
> Thanks for respinning this Ansuel, just some minor things below.
>
> > ---
> > v2:
> > * Move static varibale in msm_pinctrl struct
> > * Revert '4b024225c4a8 ("pinctrl: use
> devm_platform_ioremap_resource() to simplify code")'
> > to get base_reg addr
> >
> > drivers/pinctrl/qcom/pinctrl-msm.c | 37
> ++++++++++++++++++++++++++----
> > 1 file changed, 32 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c
> b/drivers/pinctrl/qcom/pinctrl-msm.c
> > index 9a8daa256a32..9627ebd41ff9 100644
> > --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> > @@ -22,6 +22,8 @@
> > #include <linux/reboot.h>
> > #include <linux/pm.h>
> > #include <linux/log2.h>
> > +#include <linux/qcom_scm.h>
> > +#include <linux/io.h>
> >
> > #include <linux/soc/qcom/irq.h>
> >
> > @@ -60,6 +62,9 @@ struct msm_pinctrl {
> > struct irq_chip irq_chip;
> > int irq;
> >
> > + int route_to_apps;
>
> We "always" route our interrupts to apps, so please rename this to
> intr_target_use_scm. And using "bool" instead would make it clear that
> this is a binary flag.
>
Will fix in v3
> > + u32 base_reg;
>
> Even though I think it's fine that you only fill in the first entry,
> please make this phys_base[MAX_NR_GPIO]; next to regs.
>
If I understand correctly, I should replace base_reg with
phys_base[MAX_NR_GPIO]
I think we should use MAX_NR_TILES instead of MAX_NR_GPIO
Wouldn't this be a waste of memory since only the base_reg will be needed?
I don't think there will be a soc with multiple tiles and the need to add
code
in the loop function. (Also sorry for off-topic... since we have
soc_data->ntiles
why don't we use kmem allocation instead of statically use half empty
array?)
> > +
> > raw_spinlock_t lock;
> >
> > DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
> > @@ -883,10 +888,27 @@ static int msm_gpio_irq_set_type(struct
> irq_data *d, unsigned int type)
> > clear_bit(d->hwirq, pctrl->dual_edge_irqs);
> >
> > /* Route interrupts to application cpu */
> > - val = msm_readl_intr_target(pctrl, g);
> > - val &= ~(7 << g->intr_target_bit);
> > - val |= g->intr_target_kpss_val << g->intr_target_bit;
> > - msm_writel_intr_target(val, pctrl, g);
> > + if (pctrl->route_to_apps && pctrl->base_reg) {
>
> I meant that you could fill out "base_reg" only if it's supposed to be
> used, but looking at your patch I think it's nicer to have a separate
> flag - so you can omit the check for base_reg != NULL here.
>
Since we return error if devm_ioremap_resource fails, it is good to only
check
the route_to_apps as base_reg will be set for sure?
> > + u32 addr = pctrl->base_reg + g->intr_target_reg;
> > + int ret;
> > +
> > + qcom_scm_io_readl(addr, &val);
> > +
> > + val &= ~(7 << g->intr_target_bit);
> > + val |= g->intr_target_kpss_val << g->intr_target_bit;
> > +
> > + ret = qcom_scm_io_writel(addr, val);
> > + if (ret)
> > + dev_err(pctrl->dev,
> > + "Failed routing %lu interrupt to Apps proc",
> > + d->hwirq);
> > + }
> > + } else {
> > + val = msm_readl_intr_target(pctrl, g);
> > + val &= ~(7 << g->intr_target_bit);
> > + val |= g->intr_target_kpss_val << g->intr_target_bit;
> > + msm_writel_intr_target(val, pctrl, g);
> > + }
> >
> > /* Update configuration for gpio.
> > * RAW_STATUS_EN is left on for all gpio irqs. Due to the
> > @@ -1241,6 +1263,8 @@ int msm_pinctrl_probe(struct platform_device
> *pdev,
> > pctrl->dev = &pdev->dev;
> > pctrl->soc = soc_data;
> > pctrl->chip = msm_gpio_template;
> > + pctrl->route_to_apps = of_device_is_compatible(pctrl->dev-
> >of_node,
> > + "qcom,ipq8064-pinctrl");
> >
> > raw_spin_lock_init(&pctrl->lock);
> >
> > @@ -1253,9 +1277,12 @@ int msm_pinctrl_probe(struct
> platform_device *pdev,
> > return PTR_ERR(pctrl->regs[i]);
> > }
> > } else {
> > - pctrl->regs[0] = devm_platform_ioremap_resource(pdev, 0);
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
> > if (IS_ERR(pctrl->regs[0]))
> > return PTR_ERR(pctrl->regs[0]);
> > + else
>
> No need for the else, as the "positive" case is a return.
>
Will fix in v3
> Thank you,
> Bjorn
>
> > + pctrl->base_reg = res->start;
> > }
> >
> > msm_pinctrl_setup_pm_reset(pctrl);
> > --
> > 2.25.1
> >
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