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Message-Id: <20200328135345.695622-3-robert.marko@sartura.hr>
Date: Sat, 28 Mar 2020 14:53:51 +0100
From: Robert Marko <robert.marko@...tura.hr>
To: agross@...nel.org, bjorn.andersson@...aro.org, kishon@...com,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
robh+dt@...nel.org, devicetree@...r.kernel.org
Cc: John Crispin <john@...ozen.org>,
Robert Marko <robert.marko@...tura.hr>,
Luka Perkov <luka.perkov@...tura.hr>
Subject: [PATCH v4 3/3] ARM: dts: qcom: ipq4019: add USB devicetree nodes
From: John Crispin <john@...ozen.org>
Since we now have driver for the USB PHY, lets add the necessary nodes to DTSI.
Signed-off-by: John Crispin <john@...ozen.org>
Signed-off-by: Robert Marko <robert.marko@...tura.hr>
Cc: Luka Perkov <luka.perkov@...tura.hr>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 +++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++
2 files changed, 94 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index 418f9a022336..2ee5f05d5a43 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -109,5 +109,25 @@ wifi@...0000 {
wifi@...0000 {
status = "ok";
};
+
+ usb3_ss_phy: ssphy@...00 {
+ status = "ok";
+ };
+
+ usb3_hs_phy: hsphy@...00 {
+ status = "ok";
+ };
+
+ usb3: usb3@...8800 {
+ status = "ok";
+ };
+
+ usb2_hs_phy: hsphy@...00 {
+ status = "ok";
+ };
+
+ usb2: usb2@...8800 {
+ status = "ok";
+ };
};
};
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index bfa9ce4c6e69..ee45253361cb 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -576,5 +576,79 @@ wifi1: wifi@...0000 {
"legacy";
status = "disabled";
};
+
+ usb3_ss_phy: ssphy@...00 {
+ compatible = "qcom,usb-ss-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0x9a000 0x800>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
+ reset-names = "por_rst";
+ status = "disabled";
+ };
+
+ usb3_hs_phy: hsphy@...00 {
+ compatible = "qcom,usb-hs-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0xa6000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
+ reset-names = "por_rst", "srif_rst";
+ status = "disabled";
+ };
+
+ usb3@...8800 {
+ compatible = "qcom,dwc3";
+ reg = <0x8af8800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
+ <&gcc GCC_USB3_SLEEP_CLK>,
+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
+ clock-names = "master", "sleep", "mock_utmi";
+ ranges;
+ status = "disabled";
+
+ dwc3@...0000 {
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xf8000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ };
+ };
+
+ usb2_hs_phy: hsphy@...00 {
+ compatible = "qcom,usb-hs-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0xa8000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
+ reset-names = "por_rst", "srif_rst";
+ status = "disabled";
+ };
+
+ usb2@...8800 {
+ compatible = "qcom,dwc3";
+ reg = <0x60f8800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
+ <&gcc GCC_USB2_SLEEP_CLK>,
+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
+ clock-names = "master", "sleep", "mock_utmi";
+ ranges;
+ status = "disabled";
+
+ dwc3@...0000 {
+ compatible = "snps,dwc3";
+ reg = <0x6000000 0xf8000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_hs_phy>;
+ phy-names = "usb2-phy";
+ dr_mode = "host";
+ };
+ };
};
};
--
2.26.0
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