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Date: Sat, 28 Mar 2020 09:31:07 +0800
From: kbuild test robot <lkp@...el.com>
To: Michal Simek <monstr@...str.eu>
Cc: kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org,
monstr@...str.eu, michal.simek@...inx.com, git@...inx.com,
sfr@...b.auug.org.au, marc.zyngier@....com
Subject: Re: [PATCH 2/2] powerpc: Remove Xilinx PPC405/PPC440 support
Hi Michal,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on sound/for-next robh/for-next linus/master v5.6-rc7 next-20200327]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Michal-Simek/powerpc-Remove-support-for-ppc405-440-Xilinx-platforms/20200328-034921
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=9.2.0 make.cross ARCH=powerpc
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@...el.com>
All error/warnings (new ones prefixed by >>):
arch/powerpc/xmon/ppc-opc.c:3270:55: error: 'FSL' undeclared here (not in a function)
3270 | {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
| ^~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: 'URC' undeclared here (not in a function); did you mean 'XRC'?
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:879:13: note: in expansion of macro 'VLEUIMML'
879 | #define XS6 VLEUIMML + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:880:13: note: in expansion of macro 'XS6'
880 | #define XT6 XS6
| ^~~
arch/powerpc/xmon/ppc-opc.c:884:14: note: in expansion of macro 'XT6'
884 | #define XSQ6 XT6 + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:885:14: note: in expansion of macro 'XSQ6'
885 | #define XTQ6 XSQ6
| ^~~~
arch/powerpc/xmon/ppc-opc.c:889:13: note: in expansion of macro 'XTQ6'
889 | #define XA6 XTQ6 + 1
| ^~~~
arch/powerpc/xmon/ppc-opc.c:893:13: note: in expansion of macro 'XA6'
893 | #define XB6 XA6 + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:899:14: note: in expansion of macro 'XB6'
899 | #define XB6S XB6 + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:903:13: note: in expansion of macro 'XB6S'
903 | #define XC6 XB6S + 1
| ^~~~
arch/powerpc/xmon/ppc-opc.c:907:12: note: in expansion of macro 'XC6'
907 | #define DM XC6 + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:912:14: note: in expansion of macro 'DM'
912 | #define DMEX DM + 1
| ^~
arch/powerpc/xmon/ppc-opc.c:916:13: note: in expansion of macro 'DMEX'
916 | #define UIM DMEX + 1
| ^~~~
arch/powerpc/xmon/ppc-opc.c:918:15: note: in expansion of macro 'UIM'
918 | #define UIMM2 UIM
| ^~~
arch/powerpc/xmon/ppc-opc.c:3321:62: note: in expansion of macro 'UIMM2'
3321 | {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
| ^~~~~
>> arch/powerpc/xmon/ppc-opc.c:3500:63: error: 'URT' undeclared here (not in a function); did you mean 'FRT'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| FRT
arch/powerpc/xmon/ppc-opc.c:3500:68: error: 'URA' undeclared here (not in a function); did you mean 'FRA'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| FRA
arch/powerpc/xmon/ppc-opc.c:3500:73: error: 'URB' undeclared here (not in a function); did you mean 'FRB'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| FRB
arch/powerpc/xmon/ppc-opc.c:4674:51: error: 'FCRT' undeclared here (not in a function); did you mean 'FRT'?
4674 | {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
| ^~~~
| FRT
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[105].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[105].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[106].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[106].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7070:54: note: in expansion of macro 'VLEUIMML'
7070 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[107].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7070:54: note: in expansion of macro 'VLEUIMML'
7070 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7070:54: note: in expansion of macro 'VLEUIMML'
7070 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[107].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7070:54: note: in expansion of macro 'VLEUIMML'
7070 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7071:55: note: in expansion of macro 'VLEUIMML'
7071 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[108].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7071:55: note: in expansion of macro 'VLEUIMML'
7071 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7071:55: note: in expansion of macro 'VLEUIMML'
7071 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[108].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7071:55: note: in expansion of macro 'VLEUIMML'
7071 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7072:53: note: in expansion of macro 'VLEUIMML'
7072 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[109].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7072:53: note: in expansion of macro 'VLEUIMML'
7072 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7072:53: note: in expansion of macro 'VLEUIMML'
7072 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[109].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7072:53: note: in expansion of macro 'VLEUIMML'
7072 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7073:57: note: in expansion of macro 'VLEUIMM'
7073 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[110].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7073:57: note: in expansion of macro 'VLEUIMM'
7073 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7073:57: note: in expansion of macro 'VLEUIMM'
7073 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[110].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7073:57: note: in expansion of macro 'VLEUIMM'
7073 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7074:56: note: in expansion of macro 'VLESIMM'
7074 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[111].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7074:56: note: in expansion of macro 'VLESIMM'
7074 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7074:56: note: in expansion of macro 'VLESIMM'
7074 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[111].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7074:56: note: in expansion of macro 'VLESIMM'
7074 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7075:56: note: in expansion of macro 'VLEUIMM'
7075 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[112].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7075:56: note: in expansion of macro 'VLEUIMM'
7075 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7075:56: note: in expansion of macro 'VLEUIMM'
7075 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[112].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7075:56: note: in expansion of macro 'VLEUIMM'
7075 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7076:55: note: in expansion of macro 'VLESIMM'
7076 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[113].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7076:55: note: in expansion of macro 'VLESIMM'
7076 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7076:55: note: in expansion of macro 'VLESIMM'
7076 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[113].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7076:55: note: in expansion of macro 'VLESIMM'
7076 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7077:55: note: in expansion of macro 'VLESIMM'
7077 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[114].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7077:55: note: in expansion of macro 'VLESIMM'
7077 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7077:55: note: in expansion of macro 'VLESIMM'
7077 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[114].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7077:55: note: in expansion of macro 'VLESIMM'
7077 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7078:55: note: in expansion of macro 'VLENSIMM'
7078 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[115].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7078:55: note: in expansion of macro 'VLENSIMM'
7078 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7078:55: note: in expansion of macro 'VLENSIMM'
7078 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[115].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7078:55: note: in expansion of macro 'VLENSIMM'
7078 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7079:55: note: in expansion of macro 'VLESIMM'
7079 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[116].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7079:55: note: in expansion of macro 'VLESIMM'
7079 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7079:55: note: in expansion of macro 'VLESIMM'
7079 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[116].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7079:55: note: in expansion of macro 'VLESIMM'
7079 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7080:55: note: in expansion of macro 'VLENSIMM'
7080 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[117].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7080:55: note: in expansion of macro 'VLENSIMM'
7080 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7080:55: note: in expansion of macro 'VLENSIMM'
7080 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[117].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7080:55: note: in expansion of macro 'VLENSIMM'
7080 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7081:55: note: in expansion of macro 'VLESIMM'
7081 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[118].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7081:55: note: in expansion of macro 'VLESIMM'
7081 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7081:55: note: in expansion of macro 'VLESIMM'
7081 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[118].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7081:55: note: in expansion of macro 'VLESIMM'
7081 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
vim +3500 arch/powerpc/xmon/ppc-opc.c
08d96e0b127e07 Balbir Singh 2017-02-02 3064
08d96e0b127e07 Balbir Singh 2017-02-02 3065 {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3066 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3067 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3068 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3069 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3070 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3071 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3072 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3073 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3074 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3075 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3076 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3077 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3078 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3079 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3080 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3081 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3082 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3083 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3084 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3085 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3086 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3087 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3088 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3089 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3090 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3091 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3092 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3093 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3094 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3095 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3096 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3097 {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3098 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3099 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3100 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3101 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3102 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3103 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3104 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3105 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3106 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3107 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3108 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3109 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3110 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3111 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3112 {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3113 {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3114 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3115 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3116 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3117 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3118 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3119 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3120 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3121 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3122 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3123 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3124 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3125 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3126 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3127 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3128 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3129 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3130 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3131 {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3132 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3133 {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3134 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3135 {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3136 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3137 {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3138 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3139 {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3140 {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3141 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3142 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3143 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3144 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3145 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3146 {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3147 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3148 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3149 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3150 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3151 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3152 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3153 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3154 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3155 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3156 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3157 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3158 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3159 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3160 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3161 {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3162 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3163 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3164 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3165 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3166 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3167 {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3168 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3169 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3170 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3171 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3172 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3173 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3174 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3175 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3176 {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3177 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3178 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3179 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3180 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3181 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3182 {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3183 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3184 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3185 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3186 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3187 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3188 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3189 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3190 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3191 {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3192 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3193 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3194 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3195 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3196 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3197 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3198 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3199 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3200 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3201 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3202 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3203 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3204 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3205 {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3206 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3207 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3208 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3209 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3210 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3211 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3212 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3213 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3214 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3215 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3216 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3217 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3218 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3219 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3220 {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3221 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3222 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3223 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3224 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3225 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3226 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3227 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3228 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3229 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3230 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3231 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3232 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3233 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3234 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3235 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3236 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3237 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3238 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3239 {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3240 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3241 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3242 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3243 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3244 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3245 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3246 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3247 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3248 {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3249 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3250 {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3251 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3252 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3253 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3254 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3255 {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3256 {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3257 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3258 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3259 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3260 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3261 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3262 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3263 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3264 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3265 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3266 {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3267 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3268 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3269 {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3270 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3271 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3272 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3273 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3274 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3275 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3276 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3277 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3278 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3279 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3280 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3281 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3282 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3283 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3284 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3285 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3286 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3287 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3288 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3289 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3290 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3291 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3292 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3293 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3294 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3295 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3296 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3297 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3298 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3299 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3300 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3301 {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
08d96e0b127e07 Balbir Singh 2017-02-02 3302 {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3303 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3304 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3305 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3306 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3307 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3308 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3309 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3310 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3311 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3312 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3313 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3314 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3315 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3316 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3317 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3318 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3319 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3320 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3321 {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
08d96e0b127e07 Balbir Singh 2017-02-02 3322 {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3323 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3324 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3325 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3326 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3327 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3328 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3329 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3330 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3331 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3332 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3333 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3334 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3335 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3336 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3337 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3338 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3339 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3340 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3341 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3342 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3343 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3344 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3345 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3346 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3347 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3348 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3349 {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3350 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3351 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3352 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3353 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3354 {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3355 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3356 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3357 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3358 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3359 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3360 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3361 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3362 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3363 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3364 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3365 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3366 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3367 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3368 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3369 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3370 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3371 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3372 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3373 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3374 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3375 {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3376 {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3377 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3378 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3379 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3380 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3381 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3382 {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3383 {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3384 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3385 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3386 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3387 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3388 {"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3389 {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3390 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3391 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3392 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3393 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3394 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3395 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3396 {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3397 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3398 {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3399 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3400 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3401 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3402 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3403 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3404 {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3405 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3406 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3407 {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3408 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3409 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3410 {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3411 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3412 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3413 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3414 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3415 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3416 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3417 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3418 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3419 {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3420 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3421 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3422 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3423 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3424 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3425 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3426 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3427 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3428 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3429 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3430 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3431 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3432 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3433 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3434 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3435 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3436 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3437 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3438 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3439 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3440 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3441 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3442 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3443 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3444 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3445 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3446 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3447 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3448 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3449 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3450 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3451 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3452 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3453 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3454 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3455 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3456 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3457 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3458 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3459 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3460 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3461 {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3462 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3463 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3464 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3465 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3466 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3467 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3468 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3469 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3470 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3471 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3472 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3473 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3474 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3475 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3476 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3477 {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3478 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3479 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3480 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3481 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3482 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3483 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3484 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3485 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3486 {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3487 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3488 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3489 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3490 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3491 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3492 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3493 {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3494 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3495 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3496 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3497 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3498 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3499 {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 @3500 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3501 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3502 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3503 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3504 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3505 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3506 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3507 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3508 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3509 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3510 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3511 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3512 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3513 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3514 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3515 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3516 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3517 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3518 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3519 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3520 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3521 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3522 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3523 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3524 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3525 {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3526 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3527 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3528 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3529 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3530 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3531 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3532 {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3533 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3534 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3535 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3536 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3537 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3538 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3539 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3540 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3541 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3542 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3543 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3544 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3545 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3546 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3547 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3548 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3549 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3550 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3551 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3552 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3553 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3554 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3555 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3556 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3557 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3558 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3559 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3560 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3561 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3562 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3563 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3564 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3565 {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3566 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3567 {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3568 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3569 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3570 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3571 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3572 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3573 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3574 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3575 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3576 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3577 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3578 {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3579 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3580 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3581 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3582 {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3583 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3584 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3585 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3586 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3587 {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3588 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3589 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3590 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3591 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3592 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3593 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3594 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3595 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3596 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3597 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3598 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3599 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3600 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3601 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3602 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3603 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3604 {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3605 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3606 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3607 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3608 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3609 {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3610 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3611 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3612 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3613 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3614 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3615 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3616 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3617 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3618 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3619 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3620 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3621 {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3622 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3623 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3624 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3625 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3626 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3627 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3628 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3629 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3630 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3631 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3632 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3633 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3634 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3635 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3636 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3637 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3638 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3639 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3640 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3641 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3642 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3643 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3644 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3645 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3646 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3647 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3648 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3649 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3650 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3651 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3652 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3653 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3654 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3655 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3656 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3657 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3658 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3659 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3660 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3661 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3662 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3663 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3664 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3665 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3666 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3667 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3668 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3669 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3670 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3671 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3672 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3673 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3674 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3675 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3676 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3677 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3678 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3679 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3680 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3681 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3682 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3683 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3684 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3685 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3686 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3687 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3688 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3689 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3690 {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3691 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3692 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3693 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3694 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3695 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3696 {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3697 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3698 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3699 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3700 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3701 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3702 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3703 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3704 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3705 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3706 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3707 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3708 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3709 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3710 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3711 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3712 {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3713 {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3714 {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3715 {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3716 {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3717 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3718 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3719 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3720 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3721 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3722 {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3723 {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3724 {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3725 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3726 {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
08d96e0b127e07 Balbir Singh 2017-02-02 3727 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3728 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3729 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3730 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3731 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3732 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3733 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3734 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3735 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3736 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3737 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3738 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3739 {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3740 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3741 {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
08d96e0b127e07 Balbir Singh 2017-02-02 3742 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3743 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3744 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3745 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3746 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3747 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3748 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3749 {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
08d96e0b127e07 Balbir Singh 2017-02-02 3750 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3751 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3752 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3753 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3754 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3755 {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3756 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3757 {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3758 {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3759 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3760 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3761 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3762 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3763 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3764 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3765 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3766 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3767 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3768 {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3769 {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3770 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3771 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3772 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3773 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3774 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3775 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3776 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3777 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3778 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3779 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3780 {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3781 {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3782 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3783 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3784 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3785 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3786 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3787 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3788 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3789 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3790 {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3791 {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3792 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3793 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3794 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3795 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3796 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3797 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3798 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3799 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3800 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3801
:::::: The code at line 3500 was first introduced by commit
:::::: 08d96e0b127e07c3b90e10f1939caf70b456793e powerpc/xmon: Apply binutils changes to upgrade disassembly
:::::: TO: Balbir Singh <bsingharora@...il.com>
:::::: CC: Michael Ellerman <mpe@...erman.id.au>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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