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Message-ID: <158560362665.6059.11999047251277108233.stgit@djiang5-desk3.ch.intel.com>
Date:   Mon, 30 Mar 2020 14:27:06 -0700
From:   Dave Jiang <dave.jiang@...el.com>
To:     vkoul@...nel.org, tglx@...utronix.de, mingo@...hat.com,
        bp@...en8.de, hpa@...or.com, bhelgaas@...gle.com,
        gregkh@...uxfoundation.org, arnd@...db.de
Cc:     linux-kernel@...r.kernel.org, x86@...nel.org,
        dmaengine@...r.kernel.org, dan.j.williams@...el.com,
        ashok.raj@...el.com, fenghua.yu@...el.com,
        linux-pci@...r.kernel.org, tony.luck@...el.com, jing.lin@...el.com,
        sanjay.k.kumar@...el.com
Subject: [PATCH 3/6] pci: add PCI quirk cmdmem fixup for Intel DSA device

Since there is no standard way that defines a PCI device that receives
descriptors or commands with synchronous write operations, add quirk to set
cmdmem for the Intel accelerator device that supports it.

Signed-off-by: Dave Jiang <dave.jiang@...el.com>
---
 drivers/pci/quirks.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 29f473ebf20f..ba0572b9b9c8 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5461,3 +5461,14 @@ static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
 			      PCI_CLASS_DISPLAY_VGA, 8,
 			      quirk_reset_lenovo_thinkpad_p50_nvgpu);
+
+/*
+ * Until the PCI Sig defines a standard capaiblity check that indicates a
+ * device has cmdmem with synchronous write capability, we'll add a quirk
+ * for device that supports it.
+ */
+static void device_cmdmem_fixup(struct pci_dev *pdev)
+{
+	pdev->cmdmem = 1;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0b25, device_cmdmem_fixup);

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