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Message-Id: <1585597017-30683-1-git-send-email-wcheng@codeaurora.org>
Date: Mon, 30 Mar 2020 12:36:53 -0700
From: Wesley Cheng <wcheng@...eaurora.org>
To: agross@...nel.org, bjorn.andersson@...aro.org, kishon@...com,
robh+dt@...nel.org, mark.rutland@....com, p.zabel@...gutronix.de
Cc: linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, Wesley Cheng <wcheng@...eaurora.org>
Subject: [PATCH v4 0/4] Add SS/HS-USB changes for Qualcomm SM8150 chipset
This series adds support for the Synopsis 7nm HSPHY USB driver being
used in QCOM chipsets. The HSPHY register map differs compared to
other PHY revisions. In addition, modifications and updates are done
to the QMP driver to add new registers/offsets, and to update the
initialization sequence for enabling the SSUSB path on SM8150.
Changes in v4:
- Fix POWERDOWN offset for QMP PHY exit routine, and check for
has_phy_dp_com_ctrl instead of !has_phy_com_ctrl
Changes in v3:
- Use devm_reset_control_get_exclusive instead of referencing index for
reset handle
Changes in v2:
- Fixed YAML errors caught by dt_binding_check
*** BLURB HERE ***
Jack Pham (1):
phy: qcom-qmp: Add SM8150 QMP USB3 PHY support
Wesley Cheng (3):
dt-bindings: phy: Add binding for qcom,usb-hs-7nm
phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs
phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB
.../devicetree/bindings/phy/qcom,usb-hs-7nm.yaml | 76 ++++++
drivers/phy/qualcomm/Kconfig | 10 +
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-qmp.c | 168 +++++++++++-
drivers/phy/qualcomm/phy-qcom-qmp.h | 198 +++++++++++++-
drivers/phy/qualcomm/phy-qcom-snps-7nm.c | 294 +++++++++++++++++++++
6 files changed, 742 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,usb-hs-7nm.yaml
create mode 100644 drivers/phy/qualcomm/phy-qcom-snps-7nm.c
--
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