linux-kernel - Re: [PATCH] arm64: dts: sc7180: Swap order of gpucc and sdhc

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Message-ID: <20200331165620.GF199755@google.com>
Date:   Tue, 31 Mar 2020 09:56:20 -0700
From:   Matthias Kaehlcke <mka@...omium.org>
To:     Douglas Anderson <dianders@...omium.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Mark Rutland <mark.rutland@....com>,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: sc7180: Swap order of gpucc and sdhc_2

On Tue, Mar 31, 2020 at 09:29:00AM -0700, Douglas Anderson wrote:
> Devices are supposed to be sorted by unit address.  These two got
> swapped when they landed.  Fix.
> 
> Signed-off-by: Douglas Anderson <dianders@...omium.org>
> ---
> 
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 28 ++++++++++++++--------------
>  1 file changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 998f101ad623..4bdadfd9efb9 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -1294,6 +1294,20 @@ pinconf-sd-cd {
>  			};
>  		};
>  
> +		gpucc: clock-controller@...0000 {
> +			compatible = "qcom,sc7180-gpucc";
> +			reg = <0 0x05090000 0 0x9000>;
> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> +				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> +			clock-names = "bi_tcxo",
> +				      "gcc_gpu_gpll0_clk_src",
> +				      "gcc_gpu_gpll0_div_clk_src";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <1>;
> +		};
> +
>  		sdhc_2: sdhci@...4000 {
>  			compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
>  			reg = <0 0x08804000 0 0x1000>;
> @@ -1312,20 +1326,6 @@ sdhc_2: sdhci@...4000 {
>  			status = "disabled";
>  		};
>  
> -		gpucc: clock-controller@...0000 {
> -			compatible = "qcom,sc7180-gpucc";
> -			reg = <0 0x05090000 0 0x9000>;
> -			clocks = <&rpmhcc RPMH_CXO_CLK>,
> -				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> -				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> -			clock-names = "bi_tcxo",
> -				      "gcc_gpu_gpll0_clk_src",
> -				      "gcc_gpu_gpll0_div_clk_src";
> -			#clock-cells = <1>;
> -			#reset-cells = <1>;
> -			#power-domain-cells = <1>;
> -		};
> -
>  		qspi: spi@...c000 {
>  			compatible = "qcom,qspi-v1";
>  			reg = <0 0x088dc000 0 0x600>;

Reviewed-by: Matthias Kaehlcke <mka@...omium.org>