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Message-ID: <20200331173001.GA16751@bogus>
Date: Tue, 31 Mar 2020 11:30:01 -0600
From: Rob Herring <robh@...nel.org>
To: Ansuel Smith <ansuelsmth@...il.com>
Cc: Stanimir Varbanov <svarbanov@...sol.com>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Mark Rutland <mark.rutland@....com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Andrew Murray <amurray@...goodpenguin.co.uk>,
Philipp Zabel <p.zabel@...gutronix.de>,
linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 02/12] devicetree: bindings: pci: add missing clks to
qcom,pcie
On Fri, Mar 20, 2020 at 07:34:44PM +0100, Ansuel Smith wrote:
> Document missing clks used in ipq806x soc
>
> Signed-off-by: Ansuel Smith <ansuelsmth@...il.com>
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
What a mess the clocks are for this binding...
Oh well,
Acked-by: Rob Herring <robh@...nel.org>
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> index 981b4de12807..becdbdc0fffa 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> @@ -90,6 +90,8 @@
> Definition: Should contain the following entries
> - "core" Clocks the pcie hw block
> - "phy" Clocks the pcie PHY block
> + - "aux" Clocks the pcie AUX block
> + - "ref" Clocks the pcie ref block
> - clock-names:
> Usage: required for apq8084/ipq4019
> Value type: <stringlist>
> @@ -277,8 +279,10 @@
> <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> clocks = <&gcc PCIE_A_CLK>,
> <&gcc PCIE_H_CLK>,
> - <&gcc PCIE_PHY_CLK>;
> - clock-names = "core", "iface", "phy";
> + <&gcc PCIE_PHY_CLK>,
> + <&gcc PCIE_AUX_CLK>,
> + <&gcc PCIE_ALT_REF_CLK>;
> + clock-names = "core", "iface", "phy", "aux", "ref";
> resets = <&gcc PCIE_ACLK_RESET>,
> <&gcc PCIE_HCLK_RESET>,
> <&gcc PCIE_POR_RESET>,
> --
> 2.25.1
>
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