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Message-Id: <20200331221914.2966407-4-thierry.reding@gmail.com>
Date: Wed, 1 Apr 2020 00:19:10 +0200
From: Thierry Reding <thierry.reding@...il.com>
To: Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Thierry Reding <thierry.reding@...il.com>
Cc: Rob Herring <robh+dt@...nel.org>,
Jon Hunter <jonathanh@...dia.com>, devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH v2 3/7] arm64: tegra: Order nodes by unit-address on Tegra194
From: Thierry Reding <treding@...dia.com>
The pin controller device tree node was accidentally added in the wrong
place. Move it to the correct location to keep nodes ordered by unit-
address.
Signed-off-by: Thierry Reding <treding@...dia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 64 ++++++++++++------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index f4ede86e32b4..019f66f03a97 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -45,6 +45,38 @@ gpio: gpio@...0000 {
gpio-controller;
};
+ pinmux: pinmux@...0000 {
+ compatible = "nvidia,tegra194-pinmux";
+ reg = <0x2430000 0x17000
+ 0xc300000 0x4000>;
+
+ status = "okay";
+
+ pex_rst_c5_out_state: pex_rst_c5_out {
+ pex_rst {
+ nvidia,pins = "pex_l5_rst_n_pgg1";
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,lpdr = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ };
+ };
+
+ clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
+ clkreq {
+ nvidia,pins = "pex_l5_clkreq_n_pgg0";
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,lpdr = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ };
+ };
+ };
+
ethernet@...0000 {
compatible = "nvidia,tegra194-eqos",
"nvidia,tegra186-eqos",
@@ -139,38 +171,6 @@ agic: interrupt-controller@...0000 {
};
};
- pinmux: pinmux@...0000 {
- compatible = "nvidia,tegra194-pinmux";
- reg = <0x2430000 0x17000
- 0xc300000 0x4000>;
-
- status = "okay";
-
- pex_rst_c5_out_state: pex_rst_c5_out {
- pex_rst {
- nvidia,pins = "pex_l5_rst_n_pgg1";
- nvidia,schmitt = <TEGRA_PIN_DISABLE>;
- nvidia,lpdr = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- };
- };
-
- clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
- clkreq {
- nvidia,pins = "pex_l5_clkreq_n_pgg0";
- nvidia,schmitt = <TEGRA_PIN_DISABLE>;
- nvidia,lpdr = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- };
- };
- };
-
mc: memory-controller@...0000 {
compatible = "nvidia,tegra194-mc";
reg = <0x02c00000 0x100000>,
--
2.24.1
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