lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <a4be2faf-a698-6fa9-9280-940955b74d5c@st.com>
Date:   Wed, 1 Apr 2020 10:52:06 +0200
From:   Fabrice Gasnier <fabrice.gasnier@...com>
To:     Benjamin Gaignard <benjamin.gaignard@...com>,
        <lee.jones@...aro.org>, <robh+dt@...nel.org>,
        <mark.rutland@....com>, <mcoquelin.stm32@...il.com>,
        <alexandre.torgue@...com>, <daniel.lezcano@...aro.org>,
        <tglx@...utronix.de>
CC:     <devicetree@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v6 3/6] mfd: stm32: Add defines to be used for clkevent
 purpose

On 4/1/20 10:39 AM, Benjamin Gaignard wrote:
> Add defines to be able to enable/clear irq and configure one shot mode.
> 
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@...com>
> Acked-by: Lee Jones <lee.jones@...aro.org>
> ---
>  include/linux/mfd/stm32-lptimer.h | 5 +++++
>  1 file changed, 5 insertions(+)

Hi Benjamin,

Acked-by: Fabrice Gasnier <fabrice.gasnier@...com>

Thanks,
Fabrice

> 
> diff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lptimer.h
> index 605f62264825..90b20550c1c8 100644
> --- a/include/linux/mfd/stm32-lptimer.h
> +++ b/include/linux/mfd/stm32-lptimer.h
> @@ -27,10 +27,15 @@
>  #define STM32_LPTIM_CMPOK		BIT(3)
>  
>  /* STM32_LPTIM_ICR - bit fields */
> +#define STM32_LPTIM_ARRMCF		BIT(1)
>  #define STM32_LPTIM_CMPOKCF_ARROKCF	GENMASK(4, 3)
>  
> +/* STM32_LPTIM_IER - bit flieds */
> +#define STM32_LPTIM_ARRMIE	BIT(1)
> +
>  /* STM32_LPTIM_CR - bit fields */
>  #define STM32_LPTIM_CNTSTRT	BIT(2)
> +#define STM32_LPTIM_SNGSTRT	BIT(1)
>  #define STM32_LPTIM_ENABLE	BIT(0)
>  
>  /* STM32_LPTIM_CFGR - bit fields */
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ