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Message-Id: <1585790433-31465-2-git-send-email-sherry.sun@nxp.com>
Date: Thu, 2 Apr 2020 09:20:30 +0800
From: Sherry Sun <sherry.sun@....com>
To: bp@...en8.de, mchehab@...nel.org, tony.luck@...el.com,
james.morse@....com, rrichter@...vell.com, michal.simek@...inx.com,
manish.narani@...inx.com
Cc: linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-imx@....com, frank.li@....com
Subject: [patch v3 1/4] dt-bindings: memory-controllers: Add i.MX8MP DDRC binding doc
Add documentation for i.MX8MP DDRC binding based on synopsys_edac doc,
which use the same memory-controller IP.
Signed-off-by: Sherry Sun <sherry.sun@....com>
Reviewed-by: Rob Herring <robh@...nel.org>
---
.../devicetree/bindings/memory-controllers/synopsys.txt | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
index 9d32762c47e1..4fd14ba61474 100644
--- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
@@ -6,16 +6,20 @@ bus width configurations.
The Zynq DDR ECC controller has an optional ECC support in half-bus width
(16-bit) configuration.
-These both ECC controllers correct single bit ECC errors and detect double bit
+The i.MX8MP DDR ECC controller has an ECC support in 64-bit bus width
+configurations.
+
+All the ECC controllers correct single bit ECC errors and detect double bit
ECC errors.
Required properties:
- compatible: One of:
- 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
- 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
+ - 'fsl,imx8mp-ddrc' : i.MX8MP DDR ECC controller
- reg: Should contain DDR controller registers location and length.
-Required properties for "xlnx,zynqmp-ddrc-2.40a":
+Required properties for "xlnx,zynqmp-ddrc-2.40a" and "fsl,imx8mp-ddrc":
- interrupts: Property with a value describing the interrupt number.
Example:
--
2.17.1
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