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Message-Id: <20200402121148.1767-1-ansuelsmth@gmail.com>
Date: Thu, 2 Apr 2020 14:11:37 +0200
From: Ansuel Smith <ansuelsmth@...il.com>
To: Andy Gross <agross@...nel.org>
Cc: Ansuel Smith <ansuelsmth@...il.com>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Stanimir Varbanov <svarbanov@...sol.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Andrew Murray <amurray@...goodpenguin.co.uk>,
Philipp Zabel <p.zabel@...gutronix.de>,
linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH v2 00/10] Multiple fixes in PCIe qcom driver
This contains multiple fix for PCIe qcom driver.
Some optional reset and clocks were missing.
Fix a problem with no PARF programming that cause kernel lock on load.
Add support to force gen 1 speed if needed. (due to hardware limitation)
Add ipq8064 rev 2 support that use a different tx termination offset.
v2:
* Drop iATU programming (already done in pcie init)
* Use max-link-speed instead of force-gen1 custom definition
* Drop MRRS to 256B (Can't find a realy reason why this was suggested)
* Introduce a new variant for different revision of ipq8064
Abhishek Sahu (1):
PCIe: qcom: change duplicate PCI reset to phy reset
Ansuel Smith (7):
PCIe: qcom: add missing ipq806x clocks in PCIe driver
devicetree: bindings: pci: add missing clks to qcom,pcie
PCIe: qcom: Fixed pcie_phy_clk branch issue
PCIe: qcom: add missing reset for ipq806x
devicetree: bindings: pci: add ext reset to qcom,pcie
PCIe: qcom: fix init problem with missing PARF programming
devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom,pcie
Sham Muthayyan (2):
PCIe: qcom: add ipq8064 rev2 variant and set tx term offset
PCIe: qcom: add Force GEN1 support
.../devicetree/bindings/pci/qcom,pcie.txt | 56 +++++++-
drivers/pci/controller/dwc/pcie-qcom.c | 134 +++++++++++++++---
2 files changed, 167 insertions(+), 23 deletions(-)
--
2.25.1
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