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Message-ID: <970b9e48-e38f-7e7a-3472-7dc5a4737e58@gmail.com>
Date: Thu, 2 Apr 2020 15:48:02 +0200
From: Johan Jonker <jbx6244@...il.com>
To: helen.koike@...labora.com
Cc: dafna.hirschfeld@...labora.com, devel@...verdev.osuosl.org,
devicetree@...r.kernel.org, ezequiel@...labora.com,
heiko@...ech.de, hverkuil-cisco@...all.nl,
karthik.poduval@...il.com, kernel@...labora.com,
linux-kernel@...r.kernel.org, linux-media@...r.kernel.org,
linux-rockchip@...ts.infradead.org, mark.rutland@....com,
robh+dt@...nel.org
Subject: Re: [PATCH 3/4] arm64: dts: rockchip: add rx0 mipi-phy for rk3399
Hi Helen,
> From: Helen Koike <helen.koike@...labora.com>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 33cc21fcf4c10..fc0295d2a65a1 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -1394,6 +1394,17 @@ io_domains: io-domains {
> status = "disabled";
> };
>
> + mipi_dphy_rx0: mipi-dphy-rx0 {
For Heiko sort syscon@...70000 subnodes alphabetical or reg value first?
> + compatible = "rockchip,rk3399-mipi-dphy-rx0";
> + clocks = <&cru SCLK_MIPIDPHY_REF>,
> + <&cru SCLK_DPHY_RX0_CFG>,
> + <&cru PCLK_VIO_GRF>;
Align ^
> + clock-names = "dphy-ref", "dphy-cfg", "grf";
> + power-domains = <&power RK3399_PD_VIO>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> u2phy0: usb2-phy@...0 {
> compatible = "rockchip,rk3399-usb2phy";
> reg = <0xe450 0x10>;
> --
> 2.26.0
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