| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20200406160418.27476-1-dinguyen@kernel.org>
Date: Mon, 6 Apr 2020 11:04:13 -0500
From: Dinh Nguyen <dinguyen@...nel.org>
To: linux-clk@...r.kernel.org
Cc: dinguyen@...nel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, sboyd@...nel.org,
mturquette@...libre.com, robh+dt@...nel.org, mark.rutland@....com
Subject: [PATCHv6 0/5] clk: agilex: add clock driver
Hi,
This is version 6 of the patchset to add a clock driver to the Agilex
platform.
The change from v5 is fix build error from 'make dt_binding_check'.
Thanks,
Dinh Nguyen (5):
clk: socfpga: remove clk_ops enable/disable methods
clk: socfpga: add const to _ops data structures
dt-bindings: documentation: add clock bindings information for Agilex
clk: socfpga: agilex: add clock driver for the Agilex platform
arm64: dts: agilex: populate clock dts entries
.../bindings/clock/intel,agilex.yaml | 46 ++
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 72 +++
.../boot/dts/intel/socfpga_agilex_socdk.dts | 8 +
drivers/clk/Makefile | 3 +-
drivers/clk/socfpga/Makefile | 2 +
drivers/clk/socfpga/clk-agilex.c | 454 ++++++++++++++++++
drivers/clk/socfpga/clk-pll-a10.c | 4 +-
drivers/clk/socfpga/clk-pll-s10.c | 74 ++-
drivers/clk/socfpga/clk-pll.c | 4 +-
drivers/clk/socfpga/stratix10-clk.h | 2 +
include/dt-bindings/clock/agilex-clock.h | 70 +++
11 files changed, 728 insertions(+), 11 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml
create mode 100644 drivers/clk/socfpga/clk-agilex.c
create mode 100644 include/dt-bindings/clock/agilex-clock.h
--
2.25.1
Powered by blists - more mailing lists