| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Tue, 7 Apr 2020 09:00:48 +0200
From: "H. Nikolaus Schaller" <hns@...delico.com>
To: David Airlie <airlied@...ux.ie>, Daniel Vetter <daniel@...ll.ch>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Benoît Cousson <bcousson@...libre.com>,
Tony Lindgren <tony@...mide.com>,
Paul Cercueil <paul@...pouillou.net>,
Ralf Baechle <ralf@...ux-mips.org>,
Paul Burton <paulburton@...nel.org>,
James Hogan <jhogan@...nel.org>
Cc: Philipp Rossak <embed3d@...il.com>,
"open list:DRM PANEL DRIVERS" <dri-devel@...ts.freedesktop.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-omap <linux-omap@...r.kernel.org>,
OpenPVRSGX Linux Driver Group <openpvrsgx-devgroup@...ux.org>,
Discussions about the Letux Kernel
<letux-kernel@...nphoenux.org>, kernel@...a-handheld.com,
linux-mips@...r.kernel.org
Subject: Re: [PATCH v5 1/8] dt-bindings: add img,pvrsgx.yaml for Imagination GPUs
> Am 29.03.2020 um 19:38 schrieb H. Nikolaus Schaller <hns@...delico.com>:
>
> The Imagination PVR/SGX GPU is part of several SoC from
> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo,
> Allwinner A83 and others.
>
> With this binding, we describe how the SGX processor is
> interfaced to the SoC (registers, interrupt etc.).
>
> In most cases, Clock, Reset and power management is handled
> by a parent node or elsewhere (e.g. code in the driver).
>
> Tested by make dt_binding_check dtbs_check
>
> Signed-off-by: H. Nikolaus Schaller <hns@...delico.com>
> ---
> .../devicetree/bindings/gpu/img,pvrsgx.yaml | 109 ++++++++++++++++++
> 1 file changed, 109 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
>
> diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
> new file mode 100644
> index 000000000000..aadfb2d9b012
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
> @@ -0,0 +1,109 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Imagination PVR/SGX GPU
> +
> +maintainers:
> + - H. Nikolaus Schaller <hns@...delico.com>
> +
> +description: |+
> + This binding describes the Imagination SGX5 series of 3D accelerators which
> + are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780,
> + Allwinner A83, and Intel Poulsbo and CedarView and more.
> +
> + For an extensive list see: https://en.wikipedia.org/wiki/PowerVR#Implementations
> +
> + The SGX node is usually a child node of some DT node belonging to the SoC
> + which handles clocks, reset and general address space mapping of the SGX
> + register area.
> +
> +properties:
> + compatible:
> + oneOf:
> + - description: SGX530-121 based SoC
> + items:
> + - enum:
> + - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and similar
> + - const: img,sgx530-121
> + - const: img,sgx530
> +
> + - description: SGX530-125 based SoC
> + items:
> + - enum:
> + - ti,am3352-sgx530-125 # BeagleBone Black
> + - ti,am3517-sgx530-125
> + - ti,am4-sgx530-125
> + - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz and similar
> + - ti,ti81xx-sgx530-125
> + - const: ti,omap3-sgx530-125
> + - const: img,sgx530-125
> + - const: img,sgx530
> +
> + - description: SGX535-116 based SoC
> + items:
> + - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx
> + - const: img,sgx535-116
> + - const: img,sgx535
> +
> + - description: SGX540-116 based SoC
> + items:
> + - const: intel,medfield-gma-sgx540 # Atom Z24xx
> + - const: img,sgx540-116
> + - const: img,sgx540
> +
> + - description: SGX540-120 based SoC
> + items:
> + - enum:
> + - ingenic,jz4780-sgx540-120 # CI20
> + - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar
> + - const: img,sgx540-120
> + - const: img,sgx540
> +
> + - description: SGX544-112 based SoC
> + items:
> + - const: ti,omap4-sgx544-112
> + - const: img,sgx544-112
> + - const: img,sgx544
> +
> + - description: SGX544-116 based SoC
> + items:
> + - enum:
> + - allwinner,sun8i-a83t-sgx544-116 # Banana-Pi-M3 (Allwinner A83T) and similar
Philipp Rossak reported on a different list [1] that the a83t tells to have a sgx544-115 inside.
So it needs a separate entry.
[1]: http://lists.goldelico.com/pipermail/openpvrsgx-devgroup/2020-April/000263.html
> + - ti,dra7-sgx544-116 # DRA7
> + - ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and similar
> + - const: img,sgx544-116
> + - const: img,sgx544
> +
> + - description: SGX545-116 based SoC
> + items:
> + - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500
> + - const: img,sgx545-116
> + - const: img,sgx545
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> + - |+
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + gpu: gpu@...0 {
> + compatible = "ti,omap5-sgx544-116", "img,sgx544-116", "img,sgx544";
> + reg = <0xfe00 0x200>;
> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> +...
> --
> 2.25.1
>
Powered by blists - more mailing lists