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Date: Wed, 8 Apr 2020 15:09:56 +0200 From: Robert Foss <robert.foss@...aro.org> To: agross@...nel.org, bjorn.andersson@...aro.org, robh+dt@...nel.org, catalin.marinas@....com, will@...nel.org, shawnguo@...nel.org, leoyang.li@....com, Anson.Huang@....com, olof@...om.net, leonard.crestez@....com, geert+renesas@...der.be, marcin.juszkiewicz@...aro.org, valentin.schneider@....com, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, Loic Poulain <loic.poulain@...aro.org>, Luca Weiss <luca@...tu.xyz> Cc: Robert Foss <robert.foss@...aro.org> Subject: [PATCH v4 3/6] arm64: dts: sdm845: Add i2c-qcom-cci node The sdm845 SOC ships with a CCI controller, which has two CCI/I2C buses. Signed-off-by: Robert Foss <robert.foss@...aro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@...aro.org> --- Changes since v1: - Pad addresses to 8 bytes - Sort clock_camcc by address - Change cciX pinctrl node names - Remove pinmux/pinconf nodes from pinctrl nodes - Remove clk suffix from CCI node clock-names - Give CCI i2c-bus nodes labels arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 92 ++++++++++++++++++++++ 2 files changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index a2e05926b429..8644a2f6095a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -866,3 +866,7 @@ pinconf-rx { bias-pull-up; }; }; + +&cci { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 8f926b5234d4..f3eb1dc11ac6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +#include <dt-bindings/clock/qcom,camcc-sdm845.h> #include <dt-bindings/clock/qcom,dispcc-sdm845.h> #include <dt-bindings/clock/qcom,gcc-sdm845.h> #include <dt-bindings/clock/qcom,gpucc-sdm845.h> @@ -1813,6 +1814,42 @@ tlmm: pinctrl@...0000 { gpio-ranges = <&tlmm 0 0 150>; wakeup-parent = <&pdc_intc>; + cci0_default: cci0-default { + /* SDA, SCL */ + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci0_sleep: cci0-sleep { + /* SDA, SCL */ + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + + cci1_default: cci1-default { + /* SDA, SCL */ + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci1_sleep: cci1-sleep { + /* SDA, SCL */ + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + qspi_clk: qspi-clk { pinmux { pins = "gpio95"; @@ -3194,6 +3231,61 @@ videocc: clock-controller@...0000 { #reset-cells = <1>; }; + cci: cci@...a000 { + compatible = "qcom,sdm845-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4a000 0 0x4000>; + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + clock_camcc: clock-controller@...0000 { + compatible = "qcom,sdm845-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: mdss@...0000 { compatible = "qcom,sdm845-mdss"; reg = <0 0x0ae00000 0 0x1000>; -- 2.25.1
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