linux-kernel - Re: [PATCH V1 4/4] mmc: sdhci-msm: Enable ADMA length mismatch error interrupt

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Message-ID: <520046b7-44ee-521e-ff6d-8ee72c55cd44@codeaurora.org>
Date:   Sun, 12 Apr 2020 22:36:11 +0530
From:   Veerabhadrarao Badiganti <vbadigan@...eaurora.org>
To:     adrian.hunter@...el.com, ulf.hansson@...aro.org
Cc:     bjorn.andersson@...aro.org, linux-mmc@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        Andy Gross <agross@...nel.org>
Subject: Re: [PATCH V1 4/4] mmc: sdhci-msm: Enable ADMA length mismatch error
 interrupt


On 4/12/2020 9:23 PM, Veerabhadrarao Badiganti wrote:
> ADMA_ERR_SIZE_EN bit of VENDOR_SPECIFIC_FUNC register controls
> ADMA length mismatch error interrupt. Enable it by default.
>
> And update all bit shift defines with BIT macro.
>
> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@...eaurora.org>
> ---
>   drivers/mmc/host/sdhci-msm.c | 10 +++++-----
>   1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 482045b..660e1bc 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -56,19 +56,19 @@
>   #define CORE_FLL_CYCLE_CNT	BIT(18)
>   #define CORE_DLL_CLOCK_DISABLE	BIT(21)
>   
> -#define CORE_VENDOR_SPEC_POR_VAL 0xa1c
> +#define CORE_VENDOR_SPEC_POR_VAL 0xa3c
Sorry . This should be 0xa9c, not 0xa3c. Correcting it.
>   #define CORE_CLK_PWRSAVE	BIT(1)
>   #define CORE_HC_MCLK_SEL_DFLT	(2 << 8)
>   #define CORE_HC_MCLK_SEL_HS400	(3 << 8)
>   #define CORE_HC_MCLK_SEL_MASK	(3 << 8)
> -#define CORE_IO_PAD_PWR_SWITCH_EN	(1 << 15)
> -#define CORE_IO_PAD_PWR_SWITCH  (1 << 16)
> +#define CORE_IO_PAD_PWR_SWITCH_EN	BIT(15)
> +#define CORE_IO_PAD_PWR_SWITCH	BIT(16)
>   #define CORE_HC_SELECT_IN_EN	BIT(18)
>   #define CORE_HC_SELECT_IN_HS400	(6 << 19)
>   #define CORE_HC_SELECT_IN_MASK	(7 << 19)
>   
> -#define CORE_3_0V_SUPPORT	(1 << 25)
> -#define CORE_1_8V_SUPPORT	(1 << 26)
> +#define CORE_3_0V_SUPPORT	BIT(25)
> +#define CORE_1_8V_SUPPORT	BIT(26)
>   #define CORE_VOLT_SUPPORT	(CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
>   
>   #define CORE_CSR_CDC_CTLR_CFG0		0x130