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Date: Mon, 13 Apr 2020 14:11:01 +0200
From: Matthias Brugger <matthias.bgg@...il.com>
To: Hsin-Yi Wang <hsinyi@...omium.org>,
linux-arm-kernel@...ts.infradead.org
Cc: Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
Chun-Kuang Hu <chunkuang.hu@...nel.org>,
Enric Balletbo i Serra <enric.balletbo@...labora.com>
Subject: Re: [PATCH v2] arm64: dts: mt8173: Add gce setting in mmsys and
display node
On 4/9/20 7:50 AM, Hsin-Yi Wang wrote:
> In order to use GCE function, we need add some informations
> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>
> Signed-off-by: Hsin-Yi Wang <hsinyi@...omium.org>
> Reviewed-by: Bibby Hsieh <bibby.hsieh@...iatek.com>
> ---
Applied to v5.7-next/dts64
Thanks!
> change log:
> v1->v2: align with
> 19d8e335d58a ("dt-binding: gce: remove atomic_exec in mboxes property")
> 60fa8c13ab1a ("drm/mediatek: Move gce event property to mutex device node")
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index ccb8e88a60c5..8337ba42845d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -549,7 +549,7 @@ gce: mailbox@...12000 {
> interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
> clocks = <&infracfg CLK_INFRA_GCE>;
> clock-names = "gce";
> - #mbox-cells = <3>;
> + #mbox-cells = <2>;
> };
>
> mipi_tx0: mipi-dphy@...15000 {
> @@ -916,6 +916,9 @@ mmsys: clock-controller@...00000 {
> assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
> assigned-clock-rates = <400000000>;
> #clock-cells = <1>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> };
>
> mdp_rdma0: rdma@...01000 {
> @@ -996,6 +999,7 @@ ovl0: ovl@...0c000 {
> clocks = <&mmsys CLK_MM_DISP_OVL0>;
> iommus = <&iommu M4U_PORT_DISP_OVL0>;
> mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> };
>
> ovl1: ovl@...0d000 {
> @@ -1006,6 +1010,7 @@ ovl1: ovl@...0d000 {
> clocks = <&mmsys CLK_MM_DISP_OVL1>;
> iommus = <&iommu M4U_PORT_DISP_OVL1>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> };
>
> rdma0: rdma@...0e000 {
> @@ -1016,6 +1021,7 @@ rdma0: rdma@...0e000 {
> clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> };
>
> rdma1: rdma@...0f000 {
> @@ -1026,6 +1032,7 @@ rdma1: rdma@...0f000 {
> clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> };
>
> rdma2: rdma@...10000 {
> @@ -1036,6 +1043,7 @@ rdma2: rdma@...10000 {
> clocks = <&mmsys CLK_MM_DISP_RDMA2>;
> iommus = <&iommu M4U_PORT_DISP_RDMA2>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> };
>
> wdma0: wdma@...11000 {
> @@ -1046,6 +1054,7 @@ wdma0: wdma@...11000 {
> clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> };
>
> wdma1: wdma@...12000 {
> @@ -1056,6 +1065,7 @@ wdma1: wdma@...12000 {
> clocks = <&mmsys CLK_MM_DISP_WDMA1>;
> iommus = <&iommu M4U_PORT_DISP_WDMA1>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> };
>
> color0: color@...13000 {
> @@ -1064,6 +1074,7 @@ color0: color@...13000 {
> interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
> };
>
> color1: color@...14000 {
> @@ -1072,6 +1083,7 @@ color1: color@...14000 {
> interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_COLOR1>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> };
>
> aal@...15000 {
> @@ -1080,6 +1092,7 @@ aal@...15000 {
> interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_AAL>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> };
>
> gamma@...16000 {
> @@ -1088,6 +1101,7 @@ gamma@...16000 {
> interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
> };
>
> merge@...17000 {
> @@ -1193,6 +1207,8 @@ mutex: mutex@...20000 {
> interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_MUTEX_32K>;
> + mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
> + <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
> };
>
> larb0: larb@...21000 {
>
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