linux-kernel - [PATCH 1/8] PCI: aardvark: Set controller speed from Device Tree max-link-speed

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Message-Id: <20200415160054.951-2-pali@kernel.org>
Date:   Wed, 15 Apr 2020 18:00:47 +0200
From:   Pali Rohár <pali@...nel.org>
To:     Jason Cooper <jason@...edaemon.net>, Andrew Lunn <andrew@...n.ch>,
        Gregory Clement <gregory.clement@...tlin.com>,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Andrew Murray <amurray@...goodpenguin.co.uk>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Remi Pommarel <repk@...plefau.lt>,
        Marek Behún <marek.behun@....cz>,
        Tomasz Maciej Nowak <tmn505@...il.com>,
        Xogium <contact@...ium.me>
Cc:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-pci@...r.kernel.org
Subject: [PATCH 1/8] PCI: aardvark: Set controller speed from Device Tree max-link-speed

bindings/pci/pci.txt defines standard DT property max-link-speed for
specifying PCI gen of link. Read this property from Device Tree via
of_pci_get_max_link_speed() function and use it for configuring aardvark
PCI controller gen speed. Before this change aardvark PCI gen speed was
configured always to hardcoded value gen2. When Device Tree does not
specify max-link-speed property use by default gen3 value, maximum which
aardvark PCI controller supports.

Signed-off-by: Pali Rohár <pali@...nel.org>
---
 drivers/pci/controller/pci-aardvark.c | 32 ++++++++++++++++++++++-----
 1 file changed, 27 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 2a20b649f40c..ad4f0fa57624 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -253,8 +253,30 @@ static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie)
 	}
 }
 
+static void advk_pcie_setup_link_speed(struct advk_pcie *pcie, int link_speed)
+{
+	u32 reg;
+
+	dev_info(&pcie->pdev->dev, "setup link speed to %d\n", link_speed);
+
+	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
+	reg &= ~PCIE_GEN_SEL_MSK;
+
+	if (link_speed == 3)
+		reg |= SPEED_GEN_3;
+	else if (link_speed == 2)
+		reg |= SPEED_GEN_2;
+	else
+		reg |= SPEED_GEN_1;
+
+	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+}
+
 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 {
+	struct device *dev = &pcie->pdev->dev;
+	struct device_node *node = dev->of_node;
+	int max_link_speed;
 	u32 reg;
 
 	/* Set to Direct mode */
@@ -288,11 +310,11 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 		PCIE_CORE_CTRL2_TD_ENABLE;
 	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
 
-	/* Set GEN2 */
-	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
-	reg &= ~PCIE_GEN_SEL_MSK;
-	reg |= SPEED_GEN_2;
-	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
+	/* Set max link speed */
+	max_link_speed = of_pci_get_max_link_speed(node);
+	if (max_link_speed <= 0 || max_link_speed > 3)
+		max_link_speed = 3;
+	advk_pcie_setup_link_speed(pcie, max_link_speed);
 
 	/* Set lane X1 */
 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
-- 
2.20.1