linux-kernel - Re: [PATCH 2/2] arm64: dts: imx8qxp: support scu mailbox channel

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Message-ID: <20200415055009.uxkzy4j3l24dvvyv@pengutronix.de>
Date:   Wed, 15 Apr 2020 07:50:09 +0200
From:   Oleksij Rempel <o.rempel@...gutronix.de>
To:     peng.fan@....com
Cc:     shawnguo@...nel.org, s.hauer@...gutronix.de, robh+dt@...nel.org,
        jaswinder.singh@...aro.org, linux@...pel-privat.de,
        devicetree@...r.kernel.org, Anson.Huang@....com,
        linux-kernel@...r.kernel.org, linux-imx@....com,
        kernel@...gutronix.de, festevam@...il.com,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 2/2] arm64: dts: imx8qxp: support scu mailbox channel

On Tue, Apr 14, 2020 at 09:24:28PM +0800, peng.fan@....com wrote:
> From: Peng Fan <peng.fan@....com>
> 
> With mailbox driver support i.MX8 SCU MU channel, we could
> use it to avoid trigger interrupts for each TR/RR registers
> in one MU, instead, only one RX interrupt for a recv and
> one TX interrupt for a send.
> 
> Signed-off-by: Peng Fan <peng.fan@....com>

Reviewed-by: Oleksij Rempel <o.rempel@...gutronix.de>

> ---
> 
> Note:
>  This patch needs https://patchwork.kernel.org/patch/11446659/
>  The other three patches in the patchset has been in linux-next
> 
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 18 ++++++------------
>  1 file changed, 6 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index e8ffb7590656..d1c3c98e4b39 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -141,17 +141,11 @@
>  
>  	scu {
>  		compatible = "fsl,imx-scu";
> -		mbox-names = "tx0", "tx1", "tx2", "tx3",
> -			     "rx0", "rx1", "rx2", "rx3",
> +		mbox-names = "tx0",
> +			     "rx0",
>  			     "gip3";
>  		mboxes = <&lsio_mu1 0 0
> -			  &lsio_mu1 0 1
> -			  &lsio_mu1 0 2
> -			  &lsio_mu1 0 3
>  			  &lsio_mu1 1 0
> -			  &lsio_mu1 1 1
> -			  &lsio_mu1 1 2
> -			  &lsio_mu1 1 3
>  			  &lsio_mu1 3 3>;
>  
>  		clk: clock-controller {
> @@ -548,14 +542,14 @@
>  		};
>  
>  		lsio_mu1: mailbox@...c0000 {
> -			compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +			compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
>  			reg = <0x5d1c0000 0x10000>;
>  			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
>  			#mbox-cells = <2>;
>  		};
>  
>  		lsio_mu2: mailbox@...d0000 {
> -			compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +			compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
>  			reg = <0x5d1d0000 0x10000>;
>  			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
>  			#mbox-cells = <2>;
> @@ -563,7 +557,7 @@
>  		};
>  
>  		lsio_mu3: mailbox@...e0000 {
> -			compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +			compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
>  			reg = <0x5d1e0000 0x10000>;
>  			interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
>  			#mbox-cells = <2>;
> @@ -571,7 +565,7 @@
>  		};
>  
>  		lsio_mu4: mailbox@...f0000 {
> -			compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +			compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
>  			reg = <0x5d1f0000 0x10000>;
>  			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
>  			#mbox-cells = <2>;
> -- 
> 2.16.4
> 
> 
> 

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