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Message-ID: <20200415101251.o3wi5t6xvf56xmhq@gilmour.lan>
Date: Wed, 15 Apr 2020 12:12:51 +0200
From: Maxime Ripard <maxime@...no.tech>
To: "H. Nikolaus Schaller" <hns@...delico.com>
Cc: David Airlie <airlied@...ux.ie>, Daniel Vetter <daniel@...ll.ch>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
BenoƮt Cousson <bcousson@...libre.com>,
Tony Lindgren <tony@...mide.com>,
Paul Cercueil <paul@...pouillou.net>,
Ralf Baechle <ralf@...ux-mips.org>,
Paul Burton <paulburton@...nel.org>,
James Hogan <jhogan@...nel.org>, Kukjin Kim <kgene@...nel.org>,
Krzysztof Kozlowski <krzk@...nel.org>,
Chen-Yu Tsai <wens@...e.org>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Philipp Rossak <embed3d@...il.com>,
dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-omap@...r.kernel.org,
openpvrsgx-devgroup@...ux.org, letux-kernel@...nphoenux.org,
kernel@...a-handheld.com, linux-mips@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH v6 01/12] dt-bindings: add img,pvrsgx.yaml for
Imagination GPUs
Hi,
On Wed, Apr 15, 2020 at 10:35:08AM +0200, H. Nikolaus Schaller wrote:
> The Imagination PVR/SGX GPU is part of several SoC from
> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo,
> Allwinner A83 and others.
>
> With this binding, we describe how the SGX processor is
> interfaced to the SoC (registers, interrupt etc.).
>
> In most cases, Clock, Reset and power management is handled
> by a parent node or elsewhere (e.g. code in the driver).
Wouldn't the "code in the driver" still require the clock / reset /
power domain to be set in the DT?
Maxime
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