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Message-ID: <20200417133021.GT1068@sasha-vm>
Date: Fri, 17 Apr 2020 09:30:21 -0400
From: Sasha Levin <sashal@...nel.org>
To: Andi Kleen <ak@...ux.intel.com>
Cc: "Bae, Chang Seok" <chang.seok.bae@...el.com>,
Andy Lutomirski <luto@...nel.org>,
"Metzger, Markus T" <markus.t.metzger@...el.com>,
"hpa@...or.com" <hpa@...or.com>,
Thomas Gleixner <tglx@...utronix.de>,
"bp@...en8.de" <bp@...en8.de>,
"Hansen, Dave" <dave.hansen@...el.com>,
"Luck, Tony" <tony.luck@...el.com>,
Pedro Alves <palves@...hat.com>,
Simon Marchi <simark@...ark.ca>,
"Shankar, Ravi V" <ravi.v.shankar@...el.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v9 00/17] Enable FSGSBASE instructions
On Mon, Apr 13, 2020 at 05:32:05PM -0700, Andi Kleen wrote:
>> Is my attempt at understanding the current situation correct?
>
>Yes.
>
>Nothing breaks, and it's a nice improvement for context switch
>performance, in NMI/PMU performance, and also gives user space two free
>registers to play around with.
Thomas, Andy,
Could you list your outstanding objections to this patchset? I know it
might be rehashing stuff you've already mentioned in this thread but I
think that there's a disconnect between folks and it'll help with
restarting everything.
--
Thanks,
Sasha
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