lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Fri, 17 Apr 2020 19:34:32 +0530 From: Rajendra Nayak <rnayak@...eaurora.org> To: viresh.kumar@...aro.org, sboyd@...nel.org, bjorn.andersson@...aro.org, agross@...nel.org Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, mka@...omium.org, Rajendra Nayak <rnayak@...eaurora.org> Subject: [PATCH v2 10/17] arm64: dts: sdm845: Add sdhc opps and power-domains Add the power domain supporting performance state and the corresponding OPP tables for the sdhc device on sdm845. Signed-off-by: Rajendra Nayak <rnayak@...eaurora.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 7a625ad..e6f1af1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2975,6 +2975,30 @@ }; }; + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-9600000 { + opp-hz = /bits/ 64 <9600000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-201500000 { + opp-hz = /bits/ 64 <201500000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + sdhc_2: sdhci@...4000 { compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -2987,6 +3011,8 @@ <&gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface", "core"; iommus = <&apps_smmu 0xa0 0xf>; + power-domains = <&rpmhpd SDM845_CX>; + operating-points-v2 = <&sdhc2_opp_table>; status = "disabled"; }; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Powered by blists - more mailing lists