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Message-Id: <1587132279-27659-12-git-send-email-rnayak@codeaurora.org>
Date: Fri, 17 Apr 2020 19:34:33 +0530
From: Rajendra Nayak <rnayak@...eaurora.org>
To: viresh.kumar@...aro.org, sboyd@...nel.org,
bjorn.andersson@...aro.org, agross@...nel.org
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, mka@...omium.org,
Rajendra Nayak <rnayak@...eaurora.org>
Subject: [PATCH v2 11/17] arm64: dts: sc7180: Add sdhc opps and power-domains
Add the power domain supporting performance state and the corresponding
OPP tables for the sdhc device on sdm845.
Signed-off-by: Rajendra Nayak <rnayak@...eaurora.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index db5b3b3..bcd0e6f 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -390,6 +390,20 @@
};
};
+ sdhc1_opp_table: sdhc1-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+
sdhc_1: sdhci@...000 {
compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x7c4000 0 0x1000>,
@@ -404,6 +418,8 @@
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
bus-width = <8>;
non-removable;
--
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