linux-kernel - [PATCH v2 0/4] clk: meson8b: updates for video clocks / resets

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Message-Id: <20200417184127.1319871-1-martin.blumenstingl@googlemail.com>
Date:   Fri, 17 Apr 2020 20:41:23 +0200
From:   Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To:     jbrunet@...libre.com, linux-amlogic@...ts.infradead.org,
        linux-clk@...r.kernel.org
Cc:     narmstrong@...libre.com, mturquette@...libre.com, sboyd@...nel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Subject: [PATCH v2 0/4] clk: meson8b: updates for video clocks / resets

This is the first batch of fixes and updates for the Meson8/8b/8m2
clock controller driver.

The first patch fixes the video clock hierarchy. Special thanks to
Neil for providing a lot of details about the video clock tree!

The second and third came up while testing video output on my EC-100
(Endless Mini). This board is special because u-boot does not enable
the video outputs like most other u-boot versions do. However, this
is very useful for development because it shows (the hard way ;))
where the existing code is buggy.

The last patch is a small improvement for the VPU clock so we
utilize the glitch-free mux (on SoCs which support it) and avoid
problems by changing the "live" clock tree at runtime (with the mali
clock this resulted in system hangs/freezes).

In my opinion all of these patches - including the fixes - can go to
"next" because the relevant clock trees are still read-only.

Changes since v1 at [0]:
- updated the description in patch #1 to clarify that (it seems that)
  there is no fixed pre-multiplier for the HDMI PLL (like on GXL for
  example). Spotted by Jerome - thanks!
- simplified the logic for the active_low resets in patch #2 by
  shortening the if ... else. Thanks to Jerome for the suggestion.

[0] https://patchwork.kernel.org/cover/11489079/

Martin Blumenstingl (4):
  clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
  clk: meson: meson8b: Fix the polarity of the RESET_N lines
  clk: meson: meson8b: Fix the vclk_div{1,2,4,6,12}_en gate bits
  clk: meson: meson8b: Make the CCF use the glitch-free VPU mux

 drivers/clk/meson/meson8b.c | 105 +++++++++++++++++++++++++-----------
 1 file changed, 73 insertions(+), 32 deletions(-)

-- 
2.26.1