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Message-ID: <DB6PR0402MB27608E9A3D273DCFF6D90AE888D60@DB6PR0402MB2760.eurprd04.prod.outlook.com>
Date: Sat, 18 Apr 2020 13:45:28 +0000
From: Peng Fan <peng.fan@....com>
To: "shawnguo@...nel.org" <shawnguo@...nel.org>,
"s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
Leonard Crestez <leonard.crestez@....com>,
"sboyd@...nel.org" <sboyd@...nel.org>,
Abel Vesa <abel.vesa@....com>
CC: "kernel@...gutronix.de" <kernel@...gutronix.de>,
"festevam@...il.com" <festevam@...il.com>,
dl-linux-imx <linux-imx@....com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Anson Huang <anson.huang@....com>,
Daniel Baluta <daniel.baluta@....com>,
"aford173@...il.com" <aford173@...il.com>,
Jacky Bai <ping.bai@....com>, Jun Li <jun.li@....com>,
"l.stach@...gutronix.de" <l.stach@...gutronix.de>,
"andrew.smirnov@...il.com" <andrew.smirnov@...il.com>,
"agx@...xcpu.org" <agx@...xcpu.org>,
"angus@...ea.ca" <angus@...ea.ca>,
"heiko@...ech.de" <heiko@...ech.de>,
Andy Duan <fugang.duan@....com>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
Subject: RE: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M
> Subject: [PATCH V2 00/10] clk: imx: fixes and improve for i.MX8M
Ping...
Thanks,
Peng.
>
> From: Peng Fan <peng.fan@....com>
>
> Patches based on for-next
>
> V2:
> Patch 7, drop wait after write, add one line comment for write twice
>
> V1:
> Patch 1,2 is to fix the lockdep warning reported by Leonard Patch 3 is to fix pll
> mux bit Patch 4 is align with other i.MX8M using gate Patch 5 is to simplify
> i.MX8MP clk root using composite
>
> Patch 3~5 is actually https://patchwork.kernel.org/patch/11402761/
> with a minimal change to patch 5 here.
>
> Patch 6 is to use composite core clk for A53 clk root Patch 7,8,9 is actually to
> fix CORE/BUS clk slice issue.
> This issue is triggerred after we update U-Boot to include the A53 clk fixes
> to sources from PLL, not from A53 root clk, because of the signoff timing is
> 1GHz. U-Boot set the A53 root mux to 2, sys pll2 500MHz. Kernel will set
> the A53 root mux to 4, sys pll1 800MHz, then gate off sys pll2 500MHz. Then
> kernel will gate off A53 root because clk_ignore_unsed, A53 directly sources
> PLL, so it is ok to gate off A53 root. However when gate off A53 root clk,
> system hang, because the original mux sys pll2 500MHz gated off with
> CLK_OPS_PARENT_ENABLE flag.
>
> It is lucky that we not met issue for other core/bus clk slice except A53
> ROOT core slice. But it is always triggerred after U-Boot and Linux both
> switch to use ARM PLL for A53 core, but have different mux settings for A53
> root clk slice.
>
> So the three patches is to address this issue.
>
> Patch 10 is make memrepair as critical.
>
> Peng Fan (10):
> arm64: dts: imx8m: assign clocks for A53
> clk: imx8m: drop clk_hw_set_parent for A53
> clk: imx: imx8mp: fix pll mux bit
> clk: imx8mp: Define gates for pll1/2 fixed dividers
> clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
> clk: imx8m: migrate A53 clk root to use composite core
> clk: imx: add mux ops for i.MX8M composite clk
> clk: imx: add imx8m_clk_hw_composite_bus
> clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
> clk: imx8mp: mark memrepair clock as critical
>
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 10 +-
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 10 +-
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 ++-
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 +-
> drivers/clk/imx/clk-composite-8m.c | 67 ++++++++++++-
> drivers/clk/imx/clk-imx8mm.c | 27 +++---
> drivers/clk/imx/clk-imx8mn.c | 25 +++--
> drivers/clk/imx/clk-imx8mp.c | 150
> +++++++++++++++---------------
> drivers/clk/imx/clk-imx8mq.c | 29 +++---
> drivers/clk/imx/clk.h | 7 ++
> include/dt-bindings/clock/imx8mp-clock.h | 28 +++++-
> 11 files changed, 240 insertions(+), 133 deletions(-)
>
> --
> 2.16.4
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