linux-kernel - Re: [PATCH v1 1/6] arm64: Detect the ARMv8.4 TTL feature

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Date:   Tue, 21 Apr 2020 10:16:41 -0700
From:   Christoph Hellwig <hch@...radead.org>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     Christoph Hellwig <hch@...radead.org>,
        Zhenyu Ye <yezhenyu2@...wei.com>, mark.rutland@....com,
        will@...nel.org, catalin.marinas@....com,
        aneesh.kumar@...ux.ibm.com, akpm@...ux-foundation.org,
        npiggin@...il.com, arnd@...db.de, rostedt@...dmis.org,
        maz@...nel.org, suzuki.poulose@....com, tglx@...utronix.de,
        yuzhao@...gle.com, Dave.Martin@....com, steven.price@....com,
        broonie@...nel.org, guohanjun@...wei.com,
        linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
        xiexiangyou@...wei.com, zhangshaokun@...ilicon.com,
        linux-mm@...ck.org, arm@...nel.org, prime.zeng@...ilicon.com,
        kuhn.chenqun@...wei.com, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v1 1/6] arm64: Detect the ARMv8.4 TTL feature

On Tue, Apr 21, 2020 at 07:13:28PM +0200, Peter Zijlstra wrote:
> On Tue, Apr 21, 2020 at 09:53:46AM -0700, Christoph Hellwig wrote:
> > On Fri, Apr 03, 2020 at 05:00:43PM +0800, Zhenyu Ye wrote:
> > > From: Marc Zyngier <maz@...nel.org>
> > > 
> > > In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
> > > feature allows TLBs to be issued with a level allowing for quicker
> > > invalidation.
> > 
> > What does "issued with a level" mean?
> 
> What I understood it to be is page-size based on page-table hierarchy.
> Just like we have on x86, 4k, 2m, 1g etc..
> 
> So where x86 INVLPG will tear down any sized page for the address given,
> you can now day, kill me the PMD level translation for @addr.
> 
> Power9 radix also has things like this.

Maybe this needs to be spelled out a little more?  The current commit
log sounds like paper generated by a neural network.