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Date: Tue, 21 Apr 2020 15:54:58 -0700 (PDT) From: David Miller <davem@...emloft.net> To: weifeng.voon@...el.com Cc: mcoquelin.stm32@...il.com, netdev@...r.kernel.org, linux-kernel@...r.kernel.org, joabreu@...opsys.com, peppe.cavallaro@...com, andrew@...n.ch, alexandre.torgue@...com, boon.leong.ong@...el.com Subject: Re: [net-next,v1, 1/1] net: stmmac: Enable SERDES power up/down sequence From: Voon Weifeng <weifeng.voon@...el.com> Date: Mon, 20 Apr 2020 23:42:52 +0800 > This patch is to enable Intel SERDES power up/down sequence. The SERDES > converts 8/10 bits data to SGMII signal. Below is an example of > HW configuration for SGMII mode. The SERDES is located in the PHY IF > in the diagram below. > > <-----------------GBE Controller---------->|<--External PHY chip--> > +----------+ +----+ +---+ +----------+ > | EQoS | <-GMII->| DW | < ------ > |PHY| <-SGMII-> | External | > | MAC | |xPCS| |IF | | PHY | > +----------+ +----+ +---+ +----------+ > ^ ^ ^ ^ > | | | | > +---------------------MDIO-------------------------+ > > PHY IF configuration and status registers are accessible through > mdio address 0x15 which is defined as mdio_adhoc_addr. During D0, > The driver will need to power up PHY IF by changing the power state > to P0. Likewise, for D3, the driver sets PHY IF power state to P3. > > Signed-off-by: Voon Weifeng <weifeng.voon@...el.com> > Signed-off-by: Ong Boon Leong <boon.leong.ong@...el.com> Applied, thanks.
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