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Message-Id: <1587468026-15753-1-git-send-email-wanpengli@tencent.com>
Date: Tue, 21 Apr 2020 19:20:24 +0800
From: Wanpeng Li <kernellwp@...il.com>
To: linux-kernel@...r.kernel.org, kvm@...r.kernel.org
Cc: Paolo Bonzini <pbonzini@...hat.com>,
Sean Christopherson <sean.j.christopherson@...el.com>,
Vitaly Kuznetsov <vkuznets@...hat.com>,
Wanpeng Li <wanpengli@...cent.com>,
Jim Mattson <jmattson@...gle.com>,
Joerg Roedel <joro@...tes.org>,
Haiwei Li <lihaiwei@...cent.com>
Subject: [PATCH 0/2] KVM: VMX: Tscdeadline timer emulation fastpath
IPI and Timer cause the main vmexits in cloud environment observation,
after single target IPI fastpath, let's optimize tscdeadline timer
latency by introducing tscdeadline timer emulation fastpath , it will
skip various KVM related checks when possible. i.e. after vmexit due
to tscdeadline timer emulation, handle it and vmentry immediately
without checking various kvm stuff when possible.
Testing on SKX Server.
cyclictest in guest(w/o mwait exposed, adaptive advance lapic timer is default -1):
5632.75ns -> 4559.25ns, 19%
kvm-unit-test/vmexit.flat:
w/o APICv, w/o advance timer:
tscdeadline_immed: 4780.75 -> 3851 19.4%
tscdeadline: 7474 -> 6528.5 12.7%
w/o APICv, w/ adaptive advance timer default -1:
tscdeadline_immed: 4845.75 -> 3930.5 18.9%
tscdeadline: 6048 -> 5871.75 3%
w/ APICv, w/o avanced timer:
tscdeadline_immed: 2919 -> 2467.75 15.5%
tscdeadline: 5661.75 -> 5188.25 8.4%
w/ APICv, w/ adaptive advance timer default -1:
tscdeadline_immed: 3018.5 -> 2561 15.2%
tscdeadline: 4663.75 -> 4626.5 1%
Tested-by: Haiwei Li <lihaiwei@...cent.com>
Cc: Haiwei Li <lihaiwei@...cent.com>
Wanpeng Li (2):
KVM: X86: TSCDEADLINE MSR emulation fastpath
KVM: VMX: Handle preemption timer fastpath
arch/x86/include/asm/kvm_host.h | 3 ++
arch/x86/kvm/lapic.c | 20 ++------
arch/x86/kvm/lapic.h | 16 +++++++
arch/x86/kvm/vmx/vmx.c | 101 ++++++++++++++++++++++++++++++++++++++--
arch/x86/kvm/x86.c | 55 +++++++++++++++++++---
5 files changed, 167 insertions(+), 28 deletions(-)
--
2.7.4
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