| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Thu, 23 Apr 2020 10:03:15 +0300
From: Roger Quadros <rogerq@...com>
To: Kishon Vijay Abraham I <kishon@...com>,
Rob Herring <robh@...nel.org>
CC: <t-kristo@...com>, <nm@...com>, <nsekhar@...com>,
<vigneshr@...com>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 3/6] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl
node to select SERDES lane mux
Kishon, Rob,
On 19/03/2020 13:37, Kishon Vijay Abraham I wrote:
> Hi Rob,
>
> On 11/03/20 2:39 am, Rob Herring wrote:
>> On Tue, Mar 03, 2020 at 12:17:19PM +0200, Roger Quadros wrote:
>>> From: Kishon Vijay Abraham I <kishon@...com>
>>>
>>> Add serdes_ln_ctrl node used for selecting SERDES lane mux.
>>>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
>>> Signed-off-by: Sekhar Nori <nsekhar@...com>
>>> Signed-off-by: Roger Quadros <rogerq@...com>
>>> ---
>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 27 ++++++++++++
>>> include/dt-bindings/mux/mux-j721e-wiz.h | 53 +++++++++++++++++++++++
>>> 2 files changed, 80 insertions(+)
>>> create mode 100644 include/dt-bindings/mux/mux-j721e-wiz.h
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> index cbaadee5bfdc..c5d54af37e91 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> @@ -5,6 +5,8 @@
>>> * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
>>> */
>>> #include <dt-bindings/phy/phy.h>
>>> +#include <dt-bindings/mux/mux.h>
>>> +#include <dt-bindings/mux/mux-j721e-wiz.h>
>>>
>>> &cbass_main {
>>> msmc_ram: sram@...00000 {
>>> @@ -19,6 +21,31 @@
>>> };
>>> };
>>>
>>> + scm_conf: scm-conf@...000 {
>>> + compatible = "syscon", "simple-mfd", "ti,j721e-system-controller";
>>
>> Wrong ordering. Most significant first.
>>
>>> + reg = <0 0x00100000 0 0x1c000>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0x0 0x0 0x00100000 0x1c000>;
>>> +
>>> + serdes_ln_ctrl: serdes-ln-ctrl@...0 {
>>
>> Your syscon.yaml change is not valid if you have child nodes. Do a
>> specific binding for this block.
>
> Do you mean in addition to having platform specific binding for
> scm-conf, I need to have platform specific binding for serdes-ln-ctrl.
>
> Since the driver doesn't do any platform specific stuff, the driver
> doesn't have to change. Is that correct?
>
Any resolution on this?
cheers,
-roger
> Thanks
> Kishon
>>
>>> + compatible = "mmio-mux";
>>> + reg = <0x00004080 0x50>;
>>> + #mux-control-cells = <1>;
>>> + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
>>> + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
>>> + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
>>> + <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
>>> + <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
>>> + /* SERDES4 lane0/1/2/3 select */
>>> + idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
>>> + <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
>>> + <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
>>> + <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
>>> + <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
>>> + };
>>> + };
>>> +
>>> gic500: interrupt-controller@...0000 {
>>> compatible = "arm,gic-v3";
>>> #address-cells = <2>;
>>> diff --git a/include/dt-bindings/mux/mux-j721e-wiz.h b/include/dt-bindings/mux/mux-j721e-wiz.h
>>> new file mode 100644
>>> index 000000000000..fd1c4ea9fc7f
>>> --- /dev/null
>>> +++ b/include/dt-bindings/mux/mux-j721e-wiz.h
>>> @@ -0,0 +1,53 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>> +/*
>>> + * This header provides constants for J721E WIZ.
>>> + */
>>> +
>>> +#ifndef _DT_BINDINGS_J721E_WIZ
>>> +#define _DT_BINDINGS_J721E_WIZ
>>> +
>>> +#define SERDES0_LANE0_QSGMII_LANE1 0x0
>>> +#define SERDES0_LANE0_PCIE0_LANE0 0x1
>>> +#define SERDES0_LANE0_USB3_0_SWAP 0x2
>>> +
>>> +#define SERDES0_LANE1_QSGMII_LANE2 0x0
>>> +#define SERDES0_LANE1_PCIE0_LANE1 0x1
>>> +#define SERDES0_LANE1_USB3_0 0x2
>>> +
>>> +#define SERDES1_LANE0_QSGMII_LANE3 0x0
>>> +#define SERDES1_LANE0_PCIE1_LANE0 0x1
>>> +#define SERDES1_LANE0_USB3_1_SWAP 0x2
>>> +#define SERDES1_LANE0_SGMII_LANE0 0x3
>>> +
>>> +#define SERDES1_LANE1_QSGMII_LANE4 0x0
>>> +#define SERDES1_LANE1_PCIE1_LANE1 0x1
>>> +#define SERDES1_LANE1_USB3_1 0x2
>>> +#define SERDES1_LANE1_SGMII_LANE1 0x3
>>> +
>>> +#define SERDES2_LANE0_PCIE2_LANE0 0x1
>>> +#define SERDES2_LANE0_SGMII_LANE0 0x3
>>> +#define SERDES2_LANE0_USB3_1_SWAP 0x2
>>> +
>>> +#define SERDES2_LANE1_PCIE2_LANE1 0x1
>>> +#define SERDES2_LANE1_USB3_1 0x2
>>> +#define SERDES2_LANE1_SGMII_LANE1 0x3
>>> +
>>> +#define SERDES3_LANE0_PCIE3_LANE0 0x1
>>> +#define SERDES3_LANE0_USB3_0_SWAP 0x2
>>> +
>>> +#define SERDES3_LANE1_PCIE3_LANE1 0x1
>>> +#define SERDES3_LANE1_USB3_0 0x2
>>> +
>>> +#define SERDES4_LANE0_EDP_LANE0 0x0
>>> +#define SERDES4_LANE0_QSGMII_LANE5 0x2
>>> +
>>> +#define SERDES4_LANE1_EDP_LANE1 0x0
>>> +#define SERDES4_LANE1_QSGMII_LANE6 0x2
>>> +
>>> +#define SERDES4_LANE2_EDP_LANE2 0x0
>>> +#define SERDES4_LANE2_QSGMII_LANE7 0x2
>>> +
>>> +#define SERDES4_LANE3_EDP_LANE3 0x0
>>> +#define SERDES4_LANE3_QSGMII_LANE8 0x2
>>> +
>>> +#endif /* _DT_BINDINGS_J721E_WIZ */
>>> --
>>> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
>>> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>>>
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Powered by blists - more mailing lists