linux-kernel - RE: [PATCH v2 6/9] drm/msm/a6xx: A640/A650 GMU firmware path

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Date:   Thu, 23 Apr 2020 17:36:31 +0000
From:   "Ruhl, Michael J" <michael.j.ruhl@...el.com>
To:     Jonathan Marek <jonathan@...ek.ca>,
        "freedreno@...ts.freedesktop.org" <freedreno@...ts.freedesktop.org>
CC:     Rob Clark <robdclark@...il.com>, Sean Paul <sean@...rly.run>,
        David Airlie <airlied@...ux.ie>,
        Daniel Vetter <daniel@...ll.ch>,
        Jordan Crouse <jcrouse@...eaurora.org>,
        Sharat Masetty <smasetty@...eaurora.org>,
        "open list:DRM DRIVER FOR MSM ADRENO GPU" 
        <linux-arm-msm@...r.kernel.org>,
        "open list:DRM DRIVER FOR MSM ADRENO GPU" 
        <dri-devel@...ts.freedesktop.org>,
        "open list" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 6/9] drm/msm/a6xx: A640/A650 GMU firmware path

>-----Original Message-----
>From: Jonathan Marek <jonathan@...ek.ca>
>Sent: Tuesday, April 21, 2020 7:41 PM
>To: freedreno@...ts.freedesktop.org
>Cc: Rob Clark <robdclark@...il.com>; Sean Paul <sean@...rly.run>; David
>Airlie <airlied@...ux.ie>; Daniel Vetter <daniel@...ll.ch>; Jordan Crouse
><jcrouse@...eaurora.org>; Sharat Masetty <smasetty@...eaurora.org>;
>Ruhl, Michael J <michael.j.ruhl@...el.com>; open list:DRM DRIVER FOR MSM
>ADRENO GPU <linux-arm-msm@...r.kernel.org>; open list:DRM DRIVER FOR
>MSM ADRENO GPU <dri-devel@...ts.freedesktop.org>; open list <linux-
>kernel@...r.kernel.org>
>Subject: [PATCH v2 6/9] drm/msm/a6xx: A640/A650 GMU firmware path
>
>Newer GPUs have different GMU firmware path.
>
>Signed-off-by: Jonathan Marek <jonathan@...ek.ca>
>---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c     | 135 +++++++++++++++++++-
>--
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h     |  11 ++
> drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h |   6 +
> 3 files changed, 136 insertions(+), 16 deletions(-)
>
>diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>index b22a69e2f4b0..4aef5fe985d6 100644
>--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
>@@ -571,6 +571,8 @@ static void a6xx_gmu_power_config(struct a6xx_gmu
>*gmu)
> {
> 	/* Disable GMU WB/RB buffer */
> 	gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
>+	gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
>+	gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
>
> 	gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL,
>0x9c40400);
>
>@@ -600,14 +602,91 @@ static void a6xx_gmu_power_config(struct
>a6xx_gmu *gmu)
> 		A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE);
> }
>
>+static int in_range(u32 addr, u32 start, u32 size)
>+{
>+	return addr >= start && addr < start + size;
>+}

Minor nit:

should this return a bool?

M