| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <47E9ACFA-A5DE-4918-9C79-0C50FAA6E988@goldelico.com>
Date: Fri, 24 Apr 2020 22:43:30 +0200
From: "H. Nikolaus Schaller" <hns@...delico.com>
To: Nikolaus Schaller <hns@...delico.com>
Cc: Jonathan Bakker <xc-racer2@...e.ca>,
Philipp Rossak <embed3d@...il.com>,
"open list:DRM PANEL DRIVERS" <dri-devel@...ts.freedesktop.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-omap <linux-omap@...r.kernel.org>,
OpenPVRSGX Linux Driver Group <openpvrsgx-devgroup@...ux.org>,
Discussions about the Letux Kernel
<letux-kernel@...nphoenux.org>, kernel@...a-handheld.com,
linux-mips@...r.kernel.org,
arm-soc <linux-arm-kernel@...ts.infradead.org>,
linux-samsung-soc@...r.kernel.org, David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Benoît Cousson <bcousson@...libre.com>,
Tony Lindgren <tony@...mide.com>,
Paul Cercueil <paul@...pouillou.net>,
Ralf Baechle <ralf@...ux-mips.org>,
Paul Burton <paulburton@...nel.org>,
James Hogan <jhogan@...nel.org>, Kukjin Kim <kgene@...nel.org>,
Krzysztof Kozlowski <krzk@...nel.org>,
Maxime Ripard <mripard@...nel.org>,
Chen-Yu Tsai <wens@...e.org>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Subject: Re: [PATCH v7 01/12] dt-bindings: add img,pvrsgx.yaml for Imagination GPUs
> Am 24.04.2020 um 22:34 schrieb H. Nikolaus Schaller <hns@...delico.com>:
>
> The Imagination PVR/SGX GPU is part of several SoC from
> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo,
> Allwinner A83 and others.
>
> With this binding, we describe how the SGX processor is
> interfaced to the SoC (registers and interrupt).
>
> The interface also consists of clocks, reset, power but
> information from data sheets is vague and some SoC integrators
> (TI) deciced to use a PRCM wrapper (ti,sysc) which does
s/deciced/decided/
> all clock, reset and power-management through registers
> outside of the sgx register block.
>
> Therefore all these properties are optional.
>
> Tested by make dt_binding_check
>
> Signed-off-by: H. Nikolaus Schaller <hns@...delico.com>
> ---
> .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++++++++++++++++++
> 1 file changed, 150 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
>
> diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
> new file mode 100644
> index 000000000000..33a9c4c6e784
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml
> @@ -0,0 +1,150 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Imagination PVR/SGX GPU
> +
> +maintainers:
> + - H. Nikolaus Schaller <hns@...delico.com>
> +
> +description: |+
> + This binding describes the Imagination SGX5 series of 3D accelerators which
> + are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780,
> + Allwinner A83, and Intel Poulsbo and CedarView and more.
> +
> + For an extensive list see: https://en.wikipedia.org/wiki/PowerVR#Implementations
> +
> + The SGX node is usually a child node of some DT node belonging to the SoC
> + which handles clocks, reset and general address space mapping of the SGX
> + register area. If not, an optional clock can be specified here.
^^^ this is no longer that way. now clocks, reset etc. are part of this
node but can be omitted if done by the parent node.
=> either remove this sentence or rewrite.
> +
> +properties:
> + $nodename:
> + pattern: '^gpu@[a-f0-9]+$'
> + compatible:
> + oneOf:
> + - description: SGX530-121 based SoC
> + items:
> + - enum:
> + - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and similar
> + - const: img,sgx530-121
> + - const: img,sgx530
> +
> + - description: SGX530-125 based SoC
> + items:
> + - enum:
> + - ti,am3352-sgx530-125 # BeagleBone Black
> + - ti,am3517-sgx530-125
> + - ti,am4-sgx530-125
> + - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz and similar
> + - ti,ti81xx-sgx530-125
> + - const: ti,omap3-sgx530-125
> + - const: img,sgx530-125
> + - const: img,sgx530
> +
> + - description: SGX535-116 based SoC
> + items:
> + - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx
> + - const: img,sgx535-116
> + - const: img,sgx535
> +
> + - description: SGX540-116 based SoC
> + items:
> + - const: intel,medfield-gma-sgx540 # Atom Z24xx
> + - const: img,sgx540-116
> + - const: img,sgx540
> +
> + - description: SGX540-120 based SoC
> + items:
> + - enum:
> + - samsung,s5pv210-sgx540-120
> + - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar
> + - const: img,sgx540-120
> + - const: img,sgx540
> +
> + - description: SGX540-130 based SoC
> + items:
> + - enum:
> + - ingenic,jz4780-sgx540-130 # CI20
> + - const: img,sgx540-130
> + - const: img,sgx540
> +
> + - description: SGX544-112 based SoC
> + items:
> + - const: ti,omap4470-sgx544-112
> + - const: img,sgx544-112
> + - const: img,sgx544
> +
> + - description: SGX544-115 based SoC
> + items:
> + - enum:
> + - allwinner,sun8i-a31-sgx544-115
> + - allwinner,sun8i-a31s-sgx544-115
> + - allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 (Allwinner A83T) and similar
> + - const: img,sgx544-115
> + - const: img,sgx544
> +
> + - description: SGX544-116 based SoC
> + items:
> + - enum:
> + - ti,dra7-sgx544-116 # DRA7
> + - ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and similar
> + - const: img,sgx544-116
> + - const: img,sgx544
> +
> + - description: SGX545 based SoC
> + items:
> + - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500
> + - const: img,sgx545-116
> + - const: img,sgx545
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-names:
> + maxItems: 1
> + items:
> + - const: sgx
> +
> + clocks:
> + maxItems: 4
> +
> + clock-names:
> + maxItems: 4
> + items:
> + - const: core
> + - const: sys
> + - const: mem
> + - const: hyd
> +
> + sgx-supply: true
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> + - |+
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + gpu: gpu@...0 {
> + compatible = "ti,omap5-sgx544-116", "img,sgx544-116", "img,sgx544";
> + reg = <0xfe00 0x200>;
> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> +...
> --
> 2.25.1
>
Powered by blists - more mailing lists