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Date: Fri, 24 Apr 2020 10:31:54 +0200 From: Dhananjay Kangude <dkangude@...ence.com> To: <linux-edac@...r.kernel.org> CC: <bp@...en8.de>, <mchehab@...nel.org>, <tony.luck@...el.com>, <james.morse@....com>, <linux-kernel@...r.kernel.org>, <mparab@...ence.com>, <robh+dt@...nel.org>, <devicetree@...r.kernel.org>, Dhananjay Kangude <dkangude@...ence.com> Subject: [PATCH v4 1/2] dt-bindings: edac: Add cadence ddr mc support Add documentation for cadence ddr memory controller EDAC DTS bindings Signed-off-by: Dhananjay Kangude <dkangude@...ence.com> --- .../devicetree/bindings/edac/cdns,ddr-edac.yaml | 45 ++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml diff --git a/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml new file mode 100644 index 0000000..198e60d --- /dev/null +++ b/Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/cdns,ddr-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DDR IP with ECC support (EDAC) + +description: + This binding describes the Cadence DDR/LPDDR IP with ECC feature enabled + to detect and correct CE/UE errors. + +maintainers: + - Dhananjay Kangdue <dkangude@...ence.com> + +properties: + compatible: + items: + - cdns,ddr4-mc-edac + + reg: + items: + - description: + Register block of DDR/LPDDR apb registers up to mapped area. + Mapped area contains the register set for memory controller, + phy and PI module register set doesn't part of this mapping. + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + edac: edac@...00000 { + compatible = "cdns,ddr4-mc-edac"; + reg = <0xfd100000 0x4000>; + interrupts = <0x00 0x01 0x04>; + }; +... -- 1.7.1
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