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Message-ID: <20200424084754.GI44490@ediswmail.ad.cirrus.com>
Date: Fri, 24 Apr 2020 08:47:54 +0000
From: Charles Keepax <ckeepax@...nsource.cirrus.com>
To: Shengjiu Wang <shengjiu.wang@....com>
CC: <lgirdwood@...il.com>, <broonie@...nel.org>, <perex@...ex.cz>,
<tiwai@...e.com>, <tglx@...utronix.de>, <allison@...utok.net>,
<info@...ux.net>, <patches@...nsource.cirrus.com>,
<alsa-devel@...a-project.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2] ASoC: wm8962: set CLOCKING2 as non-volatile register
On Fri, Apr 24, 2020 at 10:01:38AM +0800, Shengjiu Wang wrote:
> Previously CLOCKING2 is set as a volatile register, but cause
> issue at suspend & resume, that some bits of CLOCKING2 is not
> restored at resume, for example SYSCLK_SRC bits, then the output
> clock is wrong.
>
> The volatile property is caused by CLASSD_CLK_DIV bits,
> which are controlled by the chip itself. But the datasheet
> claims these are read only and protected by the security key,
> and they are not read by the driver at all.
>
> So it should be safe to change CLOCKING2 to be non-volatile.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@....com>
> ---
Acked-by: Charles Keepax <ckeepax@...nsource.cirrus.com>
Thanks,
Charles
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