linux-kernel - Re: [PATCH 1/2] clk: qcom: gcc: Add GPU and NPU clocks for SM8150

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Date:   Sat, 25 Apr 2020 12:10:41 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Michael Turquette <mturquette@...libre.com>,
        Vinod Koul <vkoul@...nel.org>
Cc:     linux-arm-msm@...r.kernel.org,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Vinod Koul <vkoul@...nel.org>, Andy Gross <agross@...nel.org>,
        Jonathan Marek <jonathan@...ek.ca>, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] clk: qcom: gcc: Add GPU and NPU clocks for SM8150

Quoting Vinod Koul (2020-04-23 21:43:10)
> Add the GPU and NPU clocks for SM8150. They were missed in earlier
> addition of clock driver.
> 
> Signed-off-by: Vinod Koul <vkoul@...nel.org>

Fixes tag? That way backporters know they're missing this.

> ---
>  drivers/clk/qcom/gcc-sm8150.c | 72 +++++++++++++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)
> 
> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> index ef98fdc51755..5c3dc34c955e 100644
> --- a/drivers/clk/qcom/gcc-sm8150.c
> +++ b/drivers/clk/qcom/gcc-sm8150.c
> @@ -1617,6 +1617,40 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
>         },
>  };
>  
> +/* external clocks so add BRANCH_HALT_SKIP */
> +static struct clk_branch gcc_gpu_gpll0_clk_src = {
> +       .halt_check = BRANCH_HALT_SKIP,
> +       .clkr = {
> +               .enable_reg = 0x52004,
> +               .enable_mask = BIT(15),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_gpu_gpll0_clk_src",
> +                       .parent_hws = (const struct clk_hw *[]){
> +                               &gpll0.clkr.hw },
> +                       .num_parents = 1,
> +                       .flags = CLK_SET_RATE_PARENT,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +/* these are external clocks so add BRANCH_HALT_SKIP */
> +static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
> +       .halt_check = BRANCH_HALT_SKIP,
> +       .clkr = {
> +               .enable_reg = 0x52004,
> +               .enable_mask = BIT(16),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_gpu_gpll0_div_clk_src",
> +                       .parent_hws = (const struct clk_hw *[]){
> +                               &gcc_gpu_gpll0_clk_src.clkr.hw },
> +                       .num_parents = 1,
> +                       .flags = CLK_SET_RATE_PARENT,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
>  static struct clk_branch gcc_gpu_iref_clk = {
>         .halt_reg = 0x8c010,
>         .halt_check = BRANCH_HALT,
> @@ -1699,6 +1733,40 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = {
>         },
>  };
>  
> +/* external clocks so add BRANCH_HALT_SKIP */
> +static struct clk_branch gcc_npu_gpll0_clk_src = {
> +       .halt_check = BRANCH_HALT_SKIP,
> +       .clkr = {
> +               .enable_reg = 0x52004,
> +               .enable_mask = BIT(18),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_npu_gpll0_clk_src",
> +                       .parent_hws = (const struct clk_hw *[]){
> +                               &gpll0.clkr.hw },
> +                       .num_parents = 1,
> +                       .flags = CLK_SET_RATE_PARENT,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +/* external clocks so add BRANCH_HALT_SKIP */

None of these look external. The parents are all inside this driver. Why
are we skipping the halt check?

> +static struct clk_branch gcc_npu_gpll0_div_clk_src = {
> +       .halt_check = BRANCH_HALT_SKIP,
> +       .clkr = {
> +               .enable_reg = 0x52004,
> +               .enable_mask = BIT(19),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_npu_gpll0_div_clk_src",
> +                       .parent_hws = (const struct clk_hw *[]){
> +                               &gcc_npu_gpll0_clk_src.clkr.hw },
> +                       .num_parents = 1,
> +                       .flags = CLK_SET_RATE_PARENT,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
>  static struct clk_branch gcc_npu_trig_clk = {
>         .halt_reg = 0x4d00c,
>         .halt_check = BRANCH_VOTED,