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Message-ID: <20200426134531.GB8299@alpha.franken.de>
Date: Sun, 26 Apr 2020 15:45:31 +0200
From: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
To: Tiezhu Yang <yangtiezhu@...ngson.cn>
Cc: Huacai Chen <chenhc@...ote.com>,
Jiaxun Yang <jiaxun.yang@...goat.com>,
linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org,
Xuefeng Li <lixuefeng@...ngson.cn>
Subject: Re: [PATCH] MIPS: Loongson: Add support for perf tool
On Sun, Apr 26, 2020 at 05:30:45PM +0800, Tiezhu Yang wrote:
> In order to use perf tool on the Loongson platform, we should enable kernel
> support for various performance events provided by software and hardware,
> so add CONFIG_PERF_EVENTS=y to loongson3_defconfig.
>
> E.g. without this patch:
>
> [loongson@...alhost perf]$ ./perf list
>
> List of pre-defined events (to be used in -e):
>
> duration_time [Tool event]
>
> rNNN [Raw hardware event descriptor]
> cpu/t1=v1[,t2=v2,t3 ...]/modifier [Raw hardware event descriptor]
> (see 'man perf-list' on how to encode it)
>
> mem:<addr>[/len][:access] [Hardware breakpoint]
>
> With this patch:
>
> [loongson@...alhost perf]$ ./perf list
>
> List of pre-defined events (to be used in -e):
>
> branch-instructions OR branches [Hardware event]
> branch-misses [Hardware event]
> cpu-cycles OR cycles [Hardware event]
> instructions [Hardware event]
>
> alignment-faults [Software event]
> bpf-output [Software event]
> context-switches OR cs [Software event]
> cpu-clock [Software event]
> cpu-migrations OR migrations [Software event]
> dummy [Software event]
> emulation-faults [Software event]
> major-faults [Software event]
> minor-faults [Software event]
> page-faults OR faults [Software event]
> task-clock [Software event]
>
> duration_time [Tool event]
>
> L1-dcache-load-misses [Hardware cache event]
> L1-dcache-store-misses [Hardware cache event]
> L1-icache-load-misses [Hardware cache event]
> branch-load-misses [Hardware cache event]
> branch-loads [Hardware cache event]
> dTLB-load-misses [Hardware cache event]
> dTLB-store-misses [Hardware cache event]
> iTLB-load-misses [Hardware cache event]
>
> rNNN [Raw hardware event descriptor]
> cpu/t1=v1[,t2=v2,t3 ...]/modifier [Raw hardware event descriptor]
> (see 'man perf-list' on how to encode it)
>
> mem:<addr>[/len][:access] [Hardware breakpoint]
>
> Signed-off-by: Tiezhu Yang <yangtiezhu@...ngson.cn>
> ---
> arch/mips/configs/loongson3_defconfig | 1 +
> 1 file changed, 1 insertion(+)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
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