linux-kernel - Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

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Message-ID: <VI1PR04MB694162B89953B58266395091EEAF0@VI1PR04MB6941.eurprd04.prod.outlook.com>
Date:   Mon, 27 Apr 2020 19:34:41 +0000
From:   Leonard Crestez <leonard.crestez@....com>
To:     Peng Fan <peng.fan@....com>, Anson Huang <anson.huang@....com>
CC:     "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "sboyd@...nel.org" <sboyd@...nel.org>,
        Abel Vesa <abel.vesa@....com>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        "festevam@...il.com" <festevam@...il.com>,
        dl-linux-imx <linux-imx@....com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Daniel Baluta <daniel.baluta@....com>,
        "aford173@...il.com" <aford173@...il.com>,
        Jacky Bai <ping.bai@....com>, Jun Li <jun.li@....com>,
        "l.stach@...gutronix.de" <l.stach@...gutronix.de>,
        "andrew.smirnov@...il.com" <andrew.smirnov@...il.com>,
        "agx@...xcpu.org" <agx@...xcpu.org>,
        "angus@...ea.ca" <angus@...ea.ca>,
        "heiko@...ech.de" <heiko@...ech.de>,
        Andy Duan <fugang.duan@....com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>
Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite clk

On 2020-04-27 12:15 PM, Peng Fan wrote:
>> Subject: Re: [PATCH V2 07/10] clk: imx: add mux ops for i.MX8M composite
>> clk
>>
>> On 2020-03-12 12:27 PM, Peng Fan wrote:
>>> From: Peng Fan <peng.fan@....com>
>>>
>>> The CORE/BUS root slice has following design, simplied graph:
>>> The difference is core not have pre_div block.
>>> A composite core/bus clk has 8 inputs for mux to select, saying clk[0-7].
>>>
>>>               SEL_A  GA
>>>               +--+  +-+
>>>               |  +->+ +------+
>>> CLK[0-7]--->+  |  +-+      |
>>>          |    |  |      +----v---+    +----+
>>>          |    +--+      |pre_diva+---->    |  +---------+
>>>          |              +--------+    |mux +--+post_div |
>>>          |    +--+      |pre_divb+--->+    |  +---------+
>>>          |    |  |      +----^---+    +----+
>>>          +--->+  |  +-+      |
>>>               |  +->+ +------+
>>>               +--+  +-+
>>>               SEL_B  GB
>>>
>>> There will be system hang, when doing the following steps:
>>> 1. switch mux from clk0 to clk1
>>> 2. gate off clk0
>>> 3. swtich from clk1 to clk2, or gate off clk1
>>>
>>> Step 3 triggers system hang.
>>>
>>> If we skip step2, keep clk0 on, step 3 will not trigger system hang.
>>> However we have CLK_OPS_PARENT_ENABLE flag, which will unprepare
>>> disable the clk0 which will not be used.
>>
>> As far as I understand when switching from clk1 to clk2 this is done by
>> temporarily switching the rightmost SELECT mux to whatever was in the
>> spare SEL, which is essentially arbitrary from linux POV.
> 
> No. The fixes in this patches has been confirmed by IC design owner
> 
>>
>> This is quite unexpected but in theory it might be desirable to use a third
>> parent as a fallback.
> 
> No. this will make things complicated. To CCM SEL_A and SEL_B,
> it is controlled by a hardware counter. Saying you write n times to
> the target interface.
> 
> The mux will use n % 2 to choose SEL_A or SEL_B. write twice
> to make sure SEL_A and SEL_B has the same value.

What if SEL_A and SEL_B have different values on boot? The first time 
linux does set_parent it will switch to the other SEL_X which might be off.