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Message-ID: <20200427225904.GQ7560@paulmck-ThinkPad-P72>
Date: Mon, 27 Apr 2020 15:59:04 -0700
From: "Paul E. McKenney" <paulmck@...nel.org>
To: Jon Masters <jcm@...masters.org>
Cc: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH tip/core/rcu 2/6] Documentation/memory-barriers.txt:
ACCESS_ONCE() provides cache coherence
On Thu, Apr 23, 2020 at 11:36:19PM -0400, Jon Masters wrote:
> Hi Paul,
>
> On 2/17/14 4:26 PM, Paul E. McKenney wrote:
>
> > The ACCESS_ONCE() primitive provides cache coherence, but the
> > documentation does not clearly state this. This commit therefore upgrades
> > the documentation.
>
> <snip>
>
> > + In short, ACCESS_ONCE() provides "cache coherence" for accesses from
> > + multiple CPUs to a single variable.
>
> (ACCESS_ONCE is now READ_ONCE/WRITE_ONCE but the above added the original
> language around cache coherence)
>
> I would argue that we might want to avoid describing it in this manner. The
> hardware provides cache coherency in order to keep a single memory location
> coherent between multiple observers. These kernel macros only tell the
> compiler to perform the load once. They take advantage of the properties of
> coherence in the presence of multiple observers.
You lost me on this one. Are you advocating that this be described
as constraining the compiler from invalidating the cache coherency
(single-variable sequential consistency) provided by modern hardware?
Just for background, my view is that "cache coherence", like "real time",
is a property of the system that can be destroyed by any component.
Thanx, Paul
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