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Message-ID: <CAF6AEGsEgZc=NehvFH2bRfHxcM1uR6s3sLLhk-cQPXM0SXw6Lw@mail.gmail.com>
Date: Tue, 28 Apr 2020 09:32:36 -0700
From: Rob Clark <robdclark@...il.com>
To: Rajendra Nayak <rnayak@...eaurora.org>
Cc: Viresh Kumar <viresh.kumar@...aro.org>,
Stephen Boyd <sboyd@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Andy Gross <agross@...nel.org>,
linux-arm-msm <linux-arm-msm@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Matthias Kaehlcke <mka@...omium.org>,
Sean Paul <sean@...rly.run>,
dri-devel <dri-devel@...ts.freedesktop.org>
Subject: Re: [PATCH v3 05/17] drm/msm/dpu: Use OPP API to set clk/perf state
On Tue, Apr 28, 2020 at 6:39 AM Rajendra Nayak <rnayak@...eaurora.org> wrote:
>
> On some qualcomm platforms DPU needs to express a perforamnce state
s/perforamnce/performance/
> requirement on a power domain depennding on the clock rates.
s/depennding/depending/
> Use OPP table from DT to register with OPP framework and use
> dev_pm_opp_set_rate() to set the clk/perf state.
>
> Signed-off-by: Rajendra Nayak <rnayak@...eaurora.org>
> Cc: Rob Clark <robdclark@...il.com>
> Cc: Sean Paul <sean@...rly.run>
> Cc: dri-devel@...ts.freedesktop.org
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 3 ++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 25 ++++++++++++++++++++++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 ++++
> 3 files changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> index 11f2beb..fe5717df 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
> @@ -7,6 +7,7 @@
> #include <linux/debugfs.h>
> #include <linux/errno.h>
> #include <linux/mutex.h>
> +#include <linux/pm_opp.h>
> #include <linux/sort.h>
> #include <linux/clk.h>
> #include <linux/bitmap.h>
> @@ -239,7 +240,7 @@ static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate)
> rate = core_clk->max_rate;
>
> core_clk->rate = rate;
> - return msm_dss_clk_set_rate(core_clk, 1);
> + return dev_pm_opp_set_rate(&kms->pdev->dev, core_clk->rate);
I think this leaves msm_dss_clk_set_rate() unused now?
Other than that,
Reviewed-by: Rob Clark <robdclark@...omium.org>
> }
>
> static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index ce19f1d..2f53bbf 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -10,6 +10,7 @@
> #include <linux/debugfs.h>
> #include <linux/dma-buf.h>
> #include <linux/of_irq.h>
> +#include <linux/pm_opp.h>
>
> #include <drm/drm_crtc.h>
> #include <drm/drm_file.h>
> @@ -1033,11 +1034,23 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
> if (!dpu_kms)
> return -ENOMEM;
>
> + dpu_kms->opp_table = dev_pm_opp_set_clkname(dev, "core");
> + if (IS_ERR(dpu_kms->opp_table))
> + return PTR_ERR(dpu_kms->opp_table);
> + /* OPP table is optional */
> + ret = dev_pm_opp_of_add_table(dev);
> + if (!ret) {
> + dpu_kms->has_opp_table = true;
> + } else if (ret != -ENODEV) {
> + dev_err(dev, "Invalid OPP table in Device tree\n");
> + return ret;
> + }
> +
> mp = &dpu_kms->mp;
> ret = msm_dss_parse_clock(pdev, mp);
> if (ret) {
> DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
> - return ret;
> + goto err;
> }
>
> platform_set_drvdata(pdev, dpu_kms);
> @@ -1051,6 +1064,11 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
>
> priv->kms = &dpu_kms->base;
> return ret;
> +err:
> + if (dpu_kms->has_opp_table)
> + dev_pm_opp_of_remove_table(dev);
> + dev_pm_opp_put_clkname(dpu_kms->opp_table);
> + return ret;
> }
>
> static void dpu_unbind(struct device *dev, struct device *master, void *data)
> @@ -1059,6 +1077,9 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data)
> struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
> struct dss_module_power *mp = &dpu_kms->mp;
>
> + if (dpu_kms->has_opp_table)
> + dev_pm_opp_of_remove_table(dev);
> + dev_pm_opp_put_clkname(dpu_kms->opp_table);
> msm_dss_put_clk(mp->clk_config, mp->num_clk);
> devm_kfree(&pdev->dev, mp->clk_config);
> mp->num_clk = 0;
> @@ -1090,6 +1111,8 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev)
> struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
> struct dss_module_power *mp = &dpu_kms->mp;
>
> + /* Drop the performance state vote */
> + dev_pm_opp_set_rate(dev, 0);
> rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
> if (rc)
> DPU_ERROR("clock disable failed rc:%d\n", rc);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> index 211f5de9..2a52e4e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> @@ -128,6 +128,10 @@ struct dpu_kms {
>
> struct platform_device *pdev;
> bool rpm_enabled;
> +
> + struct opp_table *opp_table;
> + bool has_opp_table;
> +
> struct dss_module_power mp;
>
> /* reference count bandwidth requests, so we know when we can
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
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