linux-kernel - Re: [PATCH 1/4] spi: lantiq: Synchronize interrupt handlers and transfers

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Message-ID: <43ecffb1-4786-c038-09bb-648657c0f5f3@linux.intel.com>
Date:   Tue, 28 Apr 2020 13:39:06 +0800
From:   Dilip Kota <eswara.kota@...ux.intel.com>
To:     Mark Brown <broonie@...nel.org>
Cc:     robh@...nel.org, linux-spi@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        daniel.schwierzeck@...il.com, hauke@...ke-m.de,
        andriy.shevchenko@...el.com, cheol.yong.kim@...el.com,
        chuanhua.lei@...ux.intel.com, qi-ming.wu@...el.com
Subject: Re: [PATCH 1/4] spi: lantiq: Synchronize interrupt handlers and
 transfers


On 4/27/2020 9:45 PM, Mark Brown wrote:
> On Mon, Apr 27, 2020 at 02:01:29PM +0800, Dilip Kota wrote:
>> On 4/24/2020 7:25 PM, Mark Brown wrote:
>>> On Fri, Apr 24, 2020 at 06:42:30PM +0800, Dilip Kota wrote:
>>>> Synchronize tx, rx and error interrupts by registering to the
>>>> same interrupt handler. Interrupt handler will recognize and process
>>>> the appropriate interrupt on the basis of interrupt status register.
>>>> Also, establish synchronization between the interrupt handler and
>>>> transfer operation by taking the locks and registering the interrupt
>>>> handler as thread IRQ which avoids the bottom half.
>>>> Fixes the wrongly populated interrupt register offsets too.
>>> This sounds like at least three different changes mixed together in one
>>> commit, it makes it quite hard to tell what's going on.  If nothing else
>>> the conversion from a workqueue to threaded interrupts should probably
>>> be split out from merging the interrupts.
>> While preparing the patches, i got puzzled to go with separate patches (for
>> threaded interrupts, unified interrupt handler and fixing the register
>> offset) or as a single patch!!.
>> Finally i choose to go with single patch, because establishing
>> synchronization is the major reason for this change, for that reason
>> threaded interrupts and unified interrupts changes are done. And the fixing
>> offset is a single line change, so included in this patch itself. And, on a
>> lighter note, the whole patch is coming under 45 lines of code changes.
>> Please let me know your view.
> The single line change to fix the offset sounds like an especially good
> candidate for splitting out as a separate patch.  It's not really about
> the number of lines but rather complexity.
Sure, i will do as separate patch.
>
>>>> -static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
>>>> +static irqreturn_t lantiq_ssc_err_interrupt(struct lantiq_ssc_spi *spi)
>>>>    {
>>>> -	struct lantiq_ssc_spi *spi = data;
>>>>    	u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
>>>> -	if (!(stat & LTQ_SPI_STAT_ERRORS))
>>>> -		return IRQ_NONE;
>>>> -
>>> Why drop this?
>> lantiq_ssc_err_interrupt() getting called, only if LTQ_SPI_IRNEN_E is set in
>> the interrupt status register.
>> Once the 'LTQ_SPI_IRNEN_E' bit is set, there is no chance of all error bits
>> being unset in the SPI_STAT register, so the 'if condition' will never be
>> successful. Hence dropped it.
> So this is another separate change and TBH it doesn't seem like a huge
> win in that it's still potentially adding a bit of robustness.
>
>>> It's not clear to me that it's a benefit to combine all the interrupts
>>> unconditionally - obviously where they're shared we need to but could
>>> that be accomplished with IRQF_SHARED and even if it can't it seems like
>>> something conditional would be better.
>> Lets take a case where Tx/Rx transfer interrupt got triggered and followed
>> by error interrupt(before finishing the tx/rx interrupt execution) which is
>> very less likely to occur, unified interrupt handler establishes
>> synchronization.
>> Comparatively, unified interrupt handler is better for adding support to the
>> latest SoCs on which SPI have single interrupt line for tx,rx and errors.
>> On basis of these two points i felt to go with unified interrupt handler.
> Does the mutex not do this regardless of how the interrupt handlers are
> wired up?
Yes, taking mutex and defining in the single ISR will be better i feel 
while adding support for multiple SoCs with different number of 
interrupt lines.

Do you suggest to use different ISRs for multiple interrupt lines and 
single ISR for single interrupt line? I see, this results in writing 
repetitive code lines.
Does single ISR looks erroneous! Please let me know.

Regards,
Dilip