linux-kernel - Re: [PATCH V2] cpufreq: imx-cpufreq-dt: support i.MX7ULP

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Message-ID: <20200428085639.6kt6qxxu44omajug@vireshk-i7>
Date:   Tue, 28 Apr 2020 14:26:39 +0530
From:   Viresh Kumar <viresh.kumar@...aro.org>
To:     peng.fan@....com
Cc:     shawnguo@...nel.org, s.hauer@...gutronix.de, rjw@...ysocki.net,
        kernel@...gutronix.de, festevam@...il.com, linux-imx@....com,
        Anson.Huang@....com, linux-pm@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2] cpufreq: imx-cpufreq-dt: support i.MX7ULP

On 28-04-20, 15:21, peng.fan@....com wrote:
> From: Peng Fan <peng.fan@....com>
> 
> i.MX7ULP's ARM core clock design is totally different compared
> with i.MX7D/8M SoCs which supported by imx-cpufreq-dt. It needs
> get_intermediate and target_intermedate to configure clk MUX ready,
> before let OPP configure ARM core clk.
>                                           |---FIRC
>      |------RUN---...---SCS(MUX2) --------|
> ARM --(MUX1)                              |---SPLL_PFD0(CLK_SET_RATE_GATE)
>      |------HSRUN--...--HSRUN_SCS(MUX3)---|
>                                           |---SRIC
> 
> FIRC is step clk, SPLL_PFD0 is the normal clk driving ARM core.
> MUX2 and MUX3 share same inputs. So if MUX2/MUX3 both sources from
> SPLL_PFD0, both MUXes will lose input when configure SPLL_PFD0.
> So the target_intermediate will configure MUX2/MUX3 to FIRC, to avoid
> ARM core lose clk when configure SPLL_PFD0.
> 
> Signed-off-by: Peng Fan <peng.fan@....com>
> ---
> 
> V2:
>  Fix boot break. Tested on i.MX8MN DDR4 EVK.

Applied. Thanks.

-- 
viresh