linux-kernel - Re: [PATCH] mmc: sdhci-pci-gli: Fix no irq handler from suspend

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 29 Apr 2020 14:14:00 +0300
From:   Adrian Hunter <adrian.hunter@...el.com>
To:     Ben Chuang <benchuanggli@...il.com>, ulf.hansson@...aro.org
Cc:     linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
        ben.chuang@...esyslogic.com.tw, Renius.Chen@...esyslogic.com.tw,
        vineethrp@...il.com, dflogeras2@...il.com
Subject: Re: [PATCH] mmc: sdhci-pci-gli: Fix no irq handler from suspend

On 27/04/20 1:30 pm, Ben Chuang wrote:
> From: Ben Chuang <ben.chuang@...esyslogic.com.tw>
> 
> The kernel prints a message similar to
> "[   28.881959] do_IRQ: 5.36 No irq handler for vector"
> when GL975x resumes from suspend. Implement a resume callback to fix this.
> 
> Fixes: 31e43f31890c ("mmc: sdhci-pci-gli: Enable MSI interrupt for GL975x")
> Co-developed-by: Renius Chen <renius.chen@...esyslogic.com.tw>
> Signed-off-by: Renius Chen <renius.chen@...esyslogic.com.tw>
> Tested-by: Dave Flogeras <dflogeras2@...il.com>
> Signed-off-by: Ben Chuang <ben.chuang@...esyslogic.com.tw>

Acked-by: Adrian Hunter <adrian.hunter@...el.com>

> ---
>  drivers/mmc/host/sdhci-pci-gli.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index ce15a05f23d4..7195dd33ac3d 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -334,6 +334,18 @@ static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
>  	return value;
>  }
>  
> +#ifdef CONFIG_PM_SLEEP
> +int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
> +{
> +	struct sdhci_pci_slot *slot = chip->slots[0];
> +
> +	pci_free_irq_vectors(slot->chip->pdev);
> +	gli_pcie_enable_msi(slot);
> +
> +	return sdhci_pci_resume_host(chip);
> +}
> +#endif
> +
>  static const struct sdhci_ops sdhci_gl9755_ops = {
>  	.set_clock		= sdhci_set_clock,
>  	.enable_dma		= sdhci_pci_enable_dma,
> @@ -348,6 +360,9 @@ const struct sdhci_pci_fixes sdhci_gl9755 = {
>  	.quirks2	= SDHCI_QUIRK2_BROKEN_DDR50,
>  	.probe_slot	= gli_probe_slot_gl9755,
>  	.ops            = &sdhci_gl9755_ops,
> +#ifdef CONFIG_PM_SLEEP
> +	.resume         = sdhci_pci_gli_resume,
> +#endif
>  };
>  
>  static const struct sdhci_ops sdhci_gl9750_ops = {
> @@ -366,4 +381,7 @@ const struct sdhci_pci_fixes sdhci_gl9750 = {
>  	.quirks2	= SDHCI_QUIRK2_BROKEN_DDR50,
>  	.probe_slot	= gli_probe_slot_gl9750,
>  	.ops            = &sdhci_gl9750_ops,
> +#ifdef CONFIG_PM_SLEEP
> +	.resume         = sdhci_pci_gli_resume,
> +#endif
>  };
>