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Date:   Wed, 29 Apr 2020 15:33:21 +0200
From:   Neil Armstrong <>
To:     Martin Blumenstingl <>
Subject: Re: [PATCH v2] drm/meson: add mode selection limits against specific
 SoC revisions


On 29/04/2020 00:03, Martin Blumenstingl wrote:
> Hi Neil,
> On Tue, Apr 28, 2020 at 11:21 AM Neil Armstrong <> wrote:
>> The Amlogic S805X/Y uses the same die as the S905X, but with more
>> limited graphics capabilities.
>> This adds a soc version detection adding specific limitations on the HDMI
>> mode selections.
>> Here, we limit to HDMI 1.3a max HDMI PHY clock frequency.
> for my own education: 1.65GHz from the PLL will be divided down to 165MHz
> isn't this more like the limit of HDMI 1.2a?

indeed from [1] :
HDMI 1.3 / 1.3a:
- Higher speed: HDMI 1.3 increases its single-link bandwidth to 340 MHz (10.2 Gbps) to support the
demands of future HD display devices, such as higher resolutions, Deep Color and high frame rates.
In addition, built into the HDMI 1.3 specification is the technical foundations that will let future
versions of HDMI reach significantly higher speeds.

So yes, it must be HDMI 1.2a, I'll fixup while applying.

>> Changes sinces v1:
>> - Moved frequency check in the vclk code, and also checks DMT modes
>> Signed-off-by: Neil Armstrong <>
> Acked-by: Martin Blumenstingl <>
> This looks good to me based on the current limitations of meson_vclk.c
> If we switch to CCF based VPU clock rate changes then we should do
> this in the clock driver by calling clk_hw_set_rate_range(hdmi_pll, 0,
> 1.65GHz)
> The good thing is: we can re-use struct meson_drm_soc_limits even
> after switching to CCF.
> We will just need to set the max PHY freq using
> clk_round_rate(hdmi_pll, ULONG_MAX)

Exact !


> Martin


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