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Message-ID: <76b5ed9c-c67b-d565-d0c0-6f2e645657ed@gmail.com>
Date: Thu, 30 Apr 2020 12:21:06 -0700
From: Florian Fainelli <f.fainelli@...il.com>
To: Jim Quinlan <james.quinlan@...adcom.com>
Cc: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Rob Herring <robh@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
"maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE"
<bcm-kernel-feedback-list@...adcom.com>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@...ts.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
"open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS"
<linux-pci@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 5/5] PCI: brcmstb: disable L0s component of ASPM by
default
On 4/30/20 11:55 AM, Jim Quinlan wrote:
> From: Jim Quinlan <jquinlan@...adcom.com>
>
> Some informal internal experiments has shown that the BrcmSTB ASPM L0s
> savings may introduce an undesirable noise signal on some customers'
> boards. In addition, L0s was found lacking in realized power savings,
> especially relative to the L1 ASPM component. This is BrcmSTB's
> experience and may not hold for others. At any rate, we disable L0s
> savings by default unless the DT node has the 'brcm,aspm-en-l0s'
> property.
>
> Signed-off-by: Jim Quinlan <jquinlan@...adcom.com>
Acked-by: Florian Fainelli <f.fainelli@...il.com>
--
Florian
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