lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Thu, 30 Apr 2020 10:36:58 +0200 From: Boris Brezillon <boris.brezillon@...labora.com> To: "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@...ux.intel.com> Cc: qi-ming.wu@...el.com, linux-kernel@...r.kernel.org, linux-mtd@...ts.infradead.org, devicetree@...r.kernel.org, cheol.yong.kim@...el.com, hauke.mehrtens@...el.com, anders.roxell@...aro.org, vigneshr@...com, arnd@...db.de, richard@....at, brendanhiggins@...gle.com, linux-mips@...r.kernel.org, robh+dt@...nel.org, miquel.raynal@...tlin.com, tglx@...utronix.de, masonccyang@...c.com.tw, andriy.shevchenko@...el.com Subject: Re: [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC On Thu, 30 Apr 2020 16:30:15 +0800 "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@...ux.intel.com> wrote: > >>> > >>> And now I'd like you to explain why 5 is the right value for that field > >>> (I guess that has to do with the position of the CS/ALE/CLE pins). > >> > >> 5 : bit 26, 25, 24, 23, 22 to be included for comparison in the > > > > That's 6 bits to me, not 5. > > No , 5 bits only the above case. Oops, right, sorry for the brain fart. > > > > The question is, is it the same value we have in nand_pa or it is > > different? > > > Different address which is 0xE1400000 NAND_BASE_PHY address. Then why didn't you tell me they didn't match when I suggested to pass nand_pa? So now the question is, what does this address represent? Do you have a reference manual I can look at to understand what this is?
Powered by blists - more mailing lists